Analog Devices Inc./Maxim Integrated MAX1071ETC+

Overview

The MAX1071ETC+ from Maxim Integrated is a 10-bit, true-differential, serial-output analog-to-digital converter (ADC) operating at up to 1.5 Msps with ±0.5 LSB INL, 61 dB SINAD at 525 kHz, and bipolar input range of ±VREF/2. It uses a single +2.7V to +3.6V analog supply, supports 1.8V–VDD digital logic via VL pin, and targets precision data acquisition in motor control and communications systems.

For engineers reviewing the MAX1071ETC+ datasheet, MAX1071ETC+ pinout, MAX1071ETC+ application, or MAX1071ETC+ equivalent, this page delivers verified electrical specs, real-world timing behavior, differential input interface constraints, power-down current values (1 µA max full shutdown), and confirmed SPI/QSPI/MICROWIRE compatibility - all specific to the MAX1071ETC+ variant.

Technical Context

The MAX1071ETC+ employs a successive-approximation register (SAR) architecture with an internal true-differential track-and-hold (T/H), enabling accurate sampling of bipolar signals without external signal conditioning. Its conversion is initiated by a CNVST falling edge and clocked by SCLK, requiring exactly 16 SCLK cycles for full 10-bit + 2 sub-bit + 3 leading zero output.

It features two low-power modes: partial power-down (1 mA typical IDD) entered after the 3rd but before the 14th SCLK rising edge, and full power-down (1 µA max IDD) entered by repeating the partial sequence. The VL pin decouples digital I/O voltage (1.8V to VDD) from analog supply, allowing direct interfacing with 1.8V logic while maintaining full-speed operation.

Key Specifications

Pinout & Package

The MAX1071ETC+ is housed in a 12-pin 3mm × 3mm TQFN package with exposed paddle (EP), rated for –40°C to +85°C operation. Pin 1 is AIN–, pin 12 is AIN+, and EP is internally connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 10-bit, high-speed, differential-input ADC applications.

Compared with ADS8326IPW and AD7457BRMZ, the MAX1071ETC+ uniquely balances 1.5 Msps throughput, true-differential bipolar input, 1.8V–VDD digital flexibility, and sub-µA shutdown - making it optimal for portable, mixed-signal, and real-time control systems where speed, interface voltage agility, and AC signal fidelity are jointly critical.

Availability

MAX1071ETC+ is available at Aetrix Electronics and suitable for motor control feedback loops, portable test equipment, communications baseband digitization, and industrial data acquisition systems requiring stable component supply across extended temperature ranges.

Supply support for MAX1071ETC+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power-management ICs for industrial, automotive, and communications applications.

The MAX1071ETC+ belongs to Maxim's high-speed, low-power SAR ADC product line, engineered specifically for applications demanding true-differential input, deterministic latency, and flexible digital I/O voltage scaling without external level shifters.

FAQ

What is the input voltage range for the MAX1071ETC+?

The MAX1071ETC+ features a true-differential bipolar input with a range of –VREF/2 to +VREF/2. With a 2.048V reference, this yields ±1.024V differential input span. Absolute input voltage on AIN+ and AIN– must remain within 0V to VDD (2.7V–3.6V) to prevent damage or conversion errors. The MAX1071ETC+ does not support unipolar input mode - that function is exclusive to the MAX1070ETC+.

Does the MAX1071ETC+ require an external reference, and what are the bypassing requirements?

Yes, the MAX1071ETC+ requires an external reference applied to the REF pin, with a valid range of +1.0V to VDD. For optimal performance, REF must be bypassed to RGND using both a 4.7µF tantalum (or low-ESR ceramic) capacitor and a 0.01µF ceramic capacitor in parallel. This dual-capacitor network suppresses low- and high-frequency noise, ensuring stable full-scale accuracy and minimizing INL drift across temperature. The MAX1071ETC+ contains no internal reference.

How does the MAX1071ETC+ enter and exit full power-down mode?

The MAX1071ETC+ enters full power-down mode by first entering partial power-down (CNVST high after the 3rd but before the 14th SCLK rising edge), then repeating the same sequence. Exit requires pulling CNVST low and waiting ≥14 SCLK cycles before pulling CNVST high again. Full power-down draws ≤1 µA total supply current. During entry/exit, SCLK must remain static (high or low) to minimize leakage. The MAX1071ETC+ does not support automatic wake-up - host control is mandatory.

Is the MAX1071ETC+ compatible with standard SPI interfaces, and what timing modes are supported?

Yes, the MAX1071ETC+ is fully compatible with SPI, QSPI, and MICROWIRE interfaces. It supports all four SPI modes (CPOL/CPHA combinations) and requires 16 SCLK cycles per conversion. Data is MSB-first, with three leading zeros, 10 data bits, two sub-bits (S1, S0), and one trailing zero. Timing is guaranteed for tCH/tCL ≥22.5 ns at VL = 1.8V and ≥18.7 ns at VL ≥2.7V. The MAX1071ETC+ does not use chip-select - CNVST serves as frame sync.

What is the role of the VL pin on the MAX1071ETC+, and can it be tied to VDD?

The VL pin supplies power to the digital I/O circuitry (CNVST, SCLK, DOUT) and sets logic thresholds (VIH/VIL). It operates from 1.8V to VDD, enabling direct interfacing with 1.8V, 2.5V, or 3.3V controllers without level shifters. VL may be tied to VDD if the host system uses the same voltage for analog and digital rails; however, doing so forfeits the key advantage of voltage-domain isolation. The MAX1071ETC+ specifies separate bypassing (10µF + 0.01µF to GND) on VL regardless of connection choice.