Analog Devices Inc./Maxim Integrated MAX1112CAP+T

Overview

MAX1112CAP+T from Maxim Integrated is an 8-bit, 8-channel successive-approximation analog-to-digital converter (ADC) with integrated track/hold, 4.096V internal reference, SPI/QSPI/MICROWIRE-compatible serial interface, and software-configurable unipolar/bipolar and single-ended/differential input modes. It operates from a single 4.5V–5.5V supply, draws only 135µA at 50ksps, and targets portable data loggers and hand-held measurement devices.

For engineers reviewing the MAX1112CAP+T datasheet, MAX1112CAP+T pinout, MAX1112CAP+T application, or MAX1112CAP+T equivalent, key selection considerations include its 8-channel single-ended input capability, 50ksps sampling rate with internal clock, ±1 LSB total unadjusted error, and 20-pin SSOP package with AGND/DGND separation for mixed-signal integrity.

Technical Context

The MAX1112CAP+T uses a capacitive DAC-based successive-approximation architecture with an internal track/hold circuit that acquires input signals in ≤1µs and completes conversion in 25µs (internal clock mode) or 10 SCLK cycles (external clock mode). Its analog front-end supports pseudo-differential sampling via channel-pair switching (e.g., CH0/CH1), with COM pin establishing zero-code reference in single-ended mode.

Control is executed via an 8-bit software-programmable command byte defining channel selection (SEL0–SEL2), unipolar/bipolar mode (UNI/BIP), single-ended/differential mode (SGL/DIF), and power-down state (PD1/PD0). The serial interface operates with CPOL=0/CPHA=0 for SPI compatibility and provides SSTRB as an end-of-conversion strobe synchronized to SCLK falling edges.

Key Specifications

Pinout & Package

The MAX1112CAP+T is housed in a 20-pin shrink small-outline package (SSOP) with exposed pad, optimized for thermal performance and PCB space efficiency in portable instrumentation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit multi-channel ADC applications.

Compared with ADS7822U and MAX1113CEE+, the MAX1112CAP+T uniquely combines 8-channel single-ended input, internal 4.096V reference, and track/hold in a single SSOP package-enabling compact, low-BOM-count data loggers without external support components.

Availability

MAX1112CAP+T is available at Aetrix Electronics and suitable for portable data logging, hand-held measurement devices, and medical instruments requiring stable component supply across extended production lifecycles.

Supply support for MAX1112CAP+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, medical, and communications applications.

The MAX1112CAP+T belongs to Maxim's precision data-acquisition product line, designed specifically for battery-operated, space-constrained systems demanding low power, integrated references, and flexible input configurations without external support circuitry.

FAQ

What is the maximum sampling rate achievable with the MAX1112CAP+T using its internal clock?

The MAX1112CAP+T achieves a maximum sampling rate of 50ksps when using its internal clock. This is confirmed in the Electrical Characteristics table under "CONVERSION RATE," where tCONV is specified as 25µs (typical) for internal clock mode - yielding 1/25µs = 40ksps typical, with 50ksps guaranteed under specified conditions (VDD = 4.5V–5.5V, fSCLK ≥ 500kHz, unipolar mode). The internal clock frequency is 400kHz (typ), supporting this rate without external timing constraints.

Does the MAX1112CAP+T support true differential input mode, or is it pseudo-differential?

The MAX1112CAP+T implements pseudo-differential input mode. As detailed in the "Detailed Description" section, the architecture samples only the positive input (IN+) while holding the negative input (IN−) stable - requiring IN− to remain within ±0.5 LSB of AGND during conversion. True differential sampling (simultaneous IN+/IN− capture) is not supported; instead, channel pairs like CH0/CH1 are switched to emulate differential behavior, with COM serving as the reference point in single-ended mode.

How does the SHDN pin function in the MAX1112CAP+T, and what are its three states?

The SHDN pin on the MAX1112CAP+T is a three-level input: high-impedance (default), pulled low, or pulled high. When high-impedance, the device operates normally and supports software power-down. Pulling SHDN low forces hardware shutdown, reducing supply current to ≤10µA. Pulling SHDN high disables the internal 4.096V reference while keeping digital circuitry active - useful when an external reference is preferred. These states are explicitly defined in the Pin Description table and confirmed in the "Power Requirements" section of the datasheet.

Can the MAX1112CAP+T interface directly with an SPI controller configured for CPOL=1 and CPHA=1?

No, the MAX1112CAP+T requires CPOL=0 and CPHA=0 for reliable SPI communication. The datasheet explicitly states in the "Simple Software Interface" section: "For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0." With CPOL=1/CPHA=1, SCLK idle state and data sampling edges misalign with MAX1112CAP+T timing - causing corrupted control bytes and invalid conversion results. MICROWIRE and QSPI modes also follow this same timing requirement.

What is the purpose of the COM pin in the MAX1112CAP+T, and how must it be connected in unipolar single-ended mode?

In unipolar single-ended mode, the COM pin serves as the zero-scale reference voltage for all analog inputs (CH0–CH7). It must be connected to AGND to establish a 0V baseline, enabling full-scale input ranges from 0V to VREFIN (4.096V). The datasheet specifies in Table 4 that "Zero Scale = COM" for unipolar mode and mandates COM stability to ±0.5 LSB - achieved by tying COM directly to AGND with low-inductance routing and avoiding shared return paths with digital currents.