Analog Devices Inc./Maxim Integrated MAX11633EEG+T

Overview

MAX11633EEG+T from Maxim Integrated is a 12-bit, 300ksps serial-output successive-approximation ADC with integrated track-and-hold, 16-channel single-ended analog multiplexer, 2.5V internal reference, and 16-entry FIFO. It operates from a +2.7V to +3.6V supply and features SPI/QSPI/MICROWIRE-compatible 3-wire interface, scan mode, internal averaging, and AutoShutdown™. It targets precision system supervision and patient monitoring where low power, channel density, and on-chip data buffering are critical.

For engineers reviewing the MAX11633EEG+T datasheet, MAX11633EEG+T pinout, MAX11633EEG+T application, or MAX11633EEG+T equivalent, key selection considerations include its 16-channel count, 2.5V internal reference accuracy (±30ppm/°C), ±1 LSB INL/DNL over –40°C to +85°C, FIFO-based burst acquisition capability, and 24-pin QSOP package compatibility with space-constrained industrial and medical PCB layouts.

Technical Context

The MAX11633EEG+T employs a SAR architecture with on-chip track-and-hold supporting unipolar 0–2.5V input range. Its internal 4.4MHz oscillator enables internally clocked conversions in modes 00, 01, and 10, while mode 11 supports externally clocked operation up to 4.8MHz for full 300ksps throughput.

It integrates configurable scan sequencing, per-channel averaging (1–16 samples), and FIFO management-allowing autonomous multi-channel acquisition without continuous μP intervention. The REF pin accepts either the internal 2.5V reference or an external 1V–VDD source, with PSRR of –70dB and output noise of 200µVRMS.

Key Specifications

Pinout & Package

MAX11633EEG+T is housed in a 24-pin QSOP (Quad Small Outline Package) with 0.154" body width and 0.025" lead pitch, optimized for automated assembly and thermal performance in compact industrial modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multichannel ADC applications.

Compared with ADS8684IPWR and AD7949BCPZ-RL7, the MAX11633EEG+T trades resolution and raw speed for integrated FIFO, ultra-low shutdown current (0.2µA), and seamless 16-channel scan sequencing - making it optimal for battery-operated, firmware-light embedded systems where deterministic acquisition timing and minimal external components are prioritized.

Availability

MAX11633EEG+T is available at Aetrix Electronics and suitable for system supervision, patient monitoring, and industrial control applications requiring stable component supply, RoHS-compliant packaging, and extended temperature support (–40°C to +85°C).

Supply support for MAX11633EEG+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, medical, and communications markets.

The MAX11633EEG+T belongs to the MAX116xx family of low-power, multichannel SAR ADCs engineered for embedded system monitoring and portable instrumentation where integration, accuracy, and power efficiency are co-optimized.

FAQ

What is the maximum sampling rate achievable with MAX11633EEG+T?

The MAX11633EEG+T achieves a maximum sampling rate of 300ksps when operating in externally clocked mode (CKSEL = 11) with a 4.8MHz SCLK. This requires disabling FIFO scan mode and averaging. At lower rates (e.g., 100ksps), internal clocking or FIFO burst acquisition can be used without sacrificing channel flexibility or power efficiency.

Does MAX11633EEG+T support differential input configurations?

No, the MAX11633EEG+T supports only single-ended analog inputs referenced to GND. Its internal architecture uses a true differential track-and-hold stage, but the negative input is hardwired to GND - resulting in unipolar 0–VREF operation. For true differential measurements, external signal conditioning (e.g., instrumentation amplifier) is required before connecting to AINx pins.

How does the FIFO function in MAX11633EEG+T during continuous scan mode?

In continuous scan mode, the MAX11633EEG+T autonomously acquires conversions into its 16-entry FIFO without host intervention. Once full, new results overwrite the oldest entries. Reading data via SPI clears entries sequentially - the oldest byte appears at DOUT after each CS falling edge. This enables gap-free acquisition at up to 300ksps while allowing the host µC to service reads at its own pace.

Can MAX11633EEG+T use an external reference, and what is the valid input range?

Yes, the MAX11633EEG+T accepts an external reference voltage applied to the REF pin. The valid range is 1.0V to VDD (2.7V–3.6V), supporting custom full-scale ranges such as 1.8V or 3.3V. When using external reference, the internal 2.5V reference is disabled, and REFSEL bits in the setup register must be configured accordingly to avoid conflict.

What is the purpose of the CNVST/AIN15 pin on MAX11633EEG+T?

The CNVST/AIN15 pin is a dual-function terminal: it serves as either the 16th analog input (AIN15) or an active-low conversion start trigger (CNVST). Configuration is controlled by the setup register. When used as CNVST, it allows hardware-triggered acquisitions independent of the SPI bus - ideal for synchronizing to external events like motor commutation edges or pulse-width modulated signals.