Analog Devices Inc./Maxim Integrated MAX1191ETI+

Overview

The MAX1191ETI+ from Maxim Integrated is an ultra-low-power, dual 8-bit analog-to-digital converter (ADC) with 7.5Msps sampling rate, fully differential 440MHz input bandwidth, and 48.6dB SINAD at 1.875MHz input frequency. It operates from a 2.7V–3.6V analog supply and 1.8V–3.6V digital supply, consuming only 12mW in normal operation. It is used in battery-powered portable instruments and low-power video acquisition systems.

For engineers reviewing the MAX1191ETI+ datasheet, MAX1191ETI+ pinout, MAX1191ETI+ application, or MAX1191ETI+ equivalent, key selection considerations include its dual-channel interleaved timing, internal/external reference flexibility, tri-state CMOS-compatible parallel outputs, and three power-down modes for dynamic power management in space-constrained embedded signal chains.

Technical Context

The MAX1191ETI+ employs a seven-stage, fully differential pipelined architecture with 5-cycle latency for Channel A and 5.5-cycle latency for Channel B. Each stage uses flash ADCs followed by DAC-based residue generation and digital error correction to ensure no missing codes and ±1 LSB INL over temperature.

Its track-and-hold circuits support both fully differential and single-ended analog inputs with matched impedance requirements and VDD/2 common-mode biasing. The internal 1.024V bandgap reference sets a ±0.512V full-scale range, while REFIN pin enables buffered or unbuffered external reference configurations with precise voltage and impedance constraints.

Key Specifications

Pinout & Package

The MAX1191ETI+ is housed in a 5mm × 5mm, 28-pin thin QFN package with exposed paddle (EP), thermally and electrically connected to GND (Pin 3). Pin 1 is INA−; pin 28 is VDD. All GND pins (3, 5, 10) and VDD pins (8, 9, 28) must be shorted externally. EP must be soldered to a solid GND plane for thermal dissipation and noise immunity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 8-bit ADC applications.

Compared with MAX1192ETI+, the MAX1191ETI+ trades 3× lower power and 3× lower cost for reduced bandwidth headroom; versus ADS8325IPW, it delivers 75× faster sampling and integrated analog front-end at the expense of DC accuracy and bit depth.

Availability

The MAX1191ETI+ is available at Aetrix Electronics and suitable for ultrasound imaging front-ends, IQ baseband sampling in wireless receivers, and battery-powered portable instrumentation requiring stable component supply across production lifecycles.

Supply support for MAX1191ETI+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for demanding industrial, medical, and communications applications.

The MAX1191ETI+ belongs to Maxim's ultra-low-power, high-speed ADC product line, engineered specifically for portable and power-sensitive signal acquisition systems where thermal envelope and battery runtime are critical constraints.

FAQ

What is the maximum analog input frequency supported by the MAX1191ETI+ while maintaining specified SINAD?

The MAX1191ETI+ maintains 48.6dB SINAD up to 1.875MHz input frequency at 7.5Msps sampling rate. At 3.75MHz input, SINAD degrades to 48.5dB. Its 440MHz small-signal bandwidth allows faithful capture of fast transients well beyond Nyquist, but dynamic specifications are guaranteed only within the first Nyquist zone (DC to 3.75MHz).

Can the MAX1191ETI+ operate with a single 3.3V supply for both analog and digital sections?

Yes - the MAX1191ETI+ supports VDD = 3.3V (within 2.7V–3.6V range) for the analog section and OVDD = 3.3V (within 1.8V–3.6V range) for the digital output drivers. This simplifies power design in 3.3V systems, though separate decoupling (2.2µF || 0.1µF per supply) is mandatory for noise-sensitive ADC performance.

How does the MAX1191ETI+ handle channel synchronization between Channel A and Channel B?

The MAX1191ETI+ uses a shared CLK input and internal pipeline architecture to ensure deterministic inter-channel timing. Channel A data appears 5 clock cycles after CLK rising edge; Channel B appears 5.5 cycles later. Amplitude matching is ±0.03dB and phase matching is ±0.03° at 1.875MHz, enabling coherent IQ sampling without external calibration.

What are the bypass capacitor requirements for the MAX1191ETI+ reference pins?

For internal or buffered external reference modes, REFP, REFN, and COM each require a 0.33µF ceramic capacitor connected directly to GND. In unbuffered external mode, the same 0.33µF capacitors apply. Additionally, REFIN requires a 0.1µF capacitor to GND in buffered external mode. All capacitors must be placed within 2mm of their respective pins.

Is an evaluation kit available for the MAX1191ETI+?

Yes - the MAX1193EVKIT evaluation kit is compatible with the MAX1191ETI+ (as stated in the datasheet). It supports all MAX1191–MAX1193 variants, providing FPGA-controlled sampling, USB data streaming, and configurable reference/input options to validate MAX1191ETI+ performance in target signal chains.