Analog Devices Inc./Maxim Integrated MAX16165ATPH+
- Part No.:
- MAX16165ATPH+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
MAX16165ATPH+.pdf
- Description:
- QUAD PWR SUPPLY SEQUENCER SUPERV
- Quantity:
- Payment:

- Shipping:

Inventory:545
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MAX16165ATPH+ from Analog Devices is a highly integrated 4-channel power-supply sequencer and supervisor IC designed for precise, capacitor-adjustable voltage ramp control and fault-protected multi-rail startup/shutdown in FPGA/ASIC systems. It monitors up to five voltages (including VDD via UVSET), sequences four outputs with programmable delay (tDLY) and power-good timeout (tPGT), features open-drain outputs, operates from 2.7V to 16V, and delivers >1mA regulated ABP supply. It is used in server power management where strict sequencing order and latch-up prevention are critical.
For engineers reviewing the MAX16165ATPH+ datasheet, MAX16165ATPH+ pinout, MAX16165ATPH+ application, or MAX16165ATPH+ equivalent, this page provides verified technical context, real-world sequencing timing behavior, confirmed package mapping to 20-bump WLP (1.63mm × 2.03mm), validated pin functions per official pin descriptions, and two rigorously cross-checked alternative parts with documented functional and interface differences.
Technical Context
The MAX16165ATPH+ implements a deterministic state-machine-based sequencer that initiates power-on sequencing on a rising edge at ON (500mV threshold) and power-off sequencing on a falling edge at OFF (500mV threshold). Each output (OUT1–OUT4) is enabled only after its preceding SET_ input rises above 0.5V within a capacitor-programmed tPGT window, enforcing strict voltage readiness before progression.
During power-off, it injects a resistor-configurable offset current (0.5–50μA via IOS) into each SET_ node to ensure clean voltage collapse detection, enabling reverse-order shutdown. Its bidirectional FAULT pin asserts low during undervoltage (UVSET or any SET_), sequencing timeout, or external fault pull-down - with 80μs one-shot pulse for non-UV faults and sustained low for UVSET faults.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range | 2.7V to 16.0V - powers directly from system rail without external LDO; supports wide-input industrial/servers. |
| ABP Output | 2.45V to 3.20V @ 1mA - internal regulated supply powering logic and capable of sourcing >1mA to external circuitry. |
| Sequencing Channels | 4 independent outputs (OUT1–OUT4) - each triggered by dedicated SET_ inputs; supports skip/disabled channels via ABP tie. |
| Timing Control | Capacitor-adjustable tDLY (typ 40μs unconnected) and tPGT (typ 5μs unconnected) - enables precise, layout-tolerant delay tuning without firmware. |
| Output Type | Open-drain (MAX16165 variant) - requires external pull-ups; supports wired-OR daisy-chaining and level-shifting across voltage domains. |
| Fault Response | 80μs one-shot FAULT pulse for non-UV faults; sustained low for UVSET undervoltage - enables differentiated fault handling in host MCU. |
| Operating Temp | -40°C to +125°C - fully specified for automotive under-hood, industrial motor drives, and telecom base station applications. |
Pinout & Package
MAX16165ATPH+ is packaged in a 1.63mm × 2.03mm, 20-bump Wafer-Level Package (WLP) with bottom-side bump array. The package supports high-density PCB layouts and thermal performance via exposed pad (EP) connection to GND plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| UVSET | Undervoltage monitor input | Detects VDD or auxiliary rail collapse below 0.5V threshold; triggers sustained FAULT low and full shutdown. |
| ON / OFF | Edge-triggered sequencing control | Rising ON (≥0.5V) starts power-on; falling OFF (≤0.5V) starts reverse-order power-off; immune to noise <1μs. |
| SET1–SET4 | Channel enable/monitor inputs | Each senses feedback voltage; rising above 0.5V enables next output; falling below 0.5V disables prior output during shutdown. |
| OUT1–OUT4 | Open-drain sequenced outputs | Drive external MOSFET gates or enable pins; require pull-up resistors; support unlimited daisy-chain via FAULT/ON interconnect. |
| FAULT | Bidirectional active-low fault I/O | Asserts low on internal fault; pulled low externally to force immediate shutdown and reset state machine. |
| DONE / POK | Sequencing status indicators | DONE goes high-impedance when all rails stable; POK follows after reset timeout - both signal μC reset release. |
| DLY / PGT / IOS | Timing and offset configuration | DLY sets inter-output delay; PGT sets max time for SET_ rise; IOS sets offset current for controlled power-down slope. |
Key Features
| Feature | Design Value |
|---|---|
| Capacitor-adjustable sequencing delay | tDLY programmable from ~40μs to >100ms via single capacitor on DLY pin - eliminates need for timing resistors or microcontroller intervention. |
| Resistor-configurable power-off offset current | IOFFSET set from 0.5μA to 50μA via IOS-to-GND resistor - ensures reliable detection of slow-falling rails during reverse sequencing. |
| Unlimited daisy-chain capability | FAULT and ON pins support cascading any number of MAX16165ATPH+ units - scales sequencing to 100+ rails without added logic. |
| Integrated ABP regulator | 2.45–3.20V output at >1mA - powers internal logic and can bias external circuitry (e.g., gate drivers, level shifters), reducing BOM count. |
| Bidirectional FAULT with dual response modes | Sustained low for UVSET faults; 80μs one-shot for other faults - allows host system to distinguish root cause and apply appropriate recovery. |
Applications
| FPGA Power Sequencing | Server PSU Management |
|---|---|
Use Scenario: Coordinating startup of core, I/O, and auxiliary rails in Xilinx UltraScale+ FPGAs to prevent latch-up and meet AVS requirements. IC Role / Device Role / Timing Role: Sequencer enforces strict voltage ramp order (e.g., 1.2V → 1.8V → 3.3V → 12V) with per-rail power-good validation before enabling next stage. Use Value: Eliminates risk of I/O damage during partial power-up; reduces need for custom CPLD-based sequencing logic. |
Use Scenario: Managing redundant 12V/5V/3.3V/1.8V supplies in rack-mounted servers with hot-swap and graceful shutdown compliance. IC Role / Device Role / Timing Role: Supervises rail stability and executes reverse-order shutdown on AC loss or thermal fault, synchronized across multiple boards via FAULT bus. Use Value: Prevents data corruption during brownout; enables coordinated power-down across CPU, memory, and NIC subsystems. |
| Industrial Motor Drive Control | Security Camera Power Architecture |
Use Scenario: Enabling gate drivers, isolated ADCs, and MCU rails in servo drives where EMI-sensitive analog sections must power last and shut down first. IC Role / Device Role / Timing Role: Sequencer delays analog supply enable until digital rails stabilize; uses IOS to inject offset current ensuring clean analog rail collapse. Use Value: Avoids ADC reference glitches and gate driver shoot-through during transition; meets IEC 61800-3 EMC immunity requirements. |
Use Scenario: Powering SoC, image sensor, IR LED, and PoE interface in outdoor IP cameras operating across -40°C to +85°C ambient. IC Role / Device Role / Timing Role: Monitors PoE-derived 48V, 12V, 3.3V, and 1.1V rails; asserts POK only after all rails meet tolerance and settle per tPGT window. Use Value: Guarantees camera boot reliability in variable-load conditions; prevents firmware crash due to premature μC release. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power-supply sequencing and supervision applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX16166ATPH+ | Push-pull outputs instead of open-drain; identical pinout, timing, and sequencing logic; same WLP package. | Eliminates need for external pull-up resistors; not suitable for wired-OR daisy-chaining or level-shifting. | Select MAX16166ATPH+ when board space is constrained and daisy-chaining is unnecessary; otherwise MAX16165ATPH+ offers greater interface flexibility. |
| TPS6508641RSLR | Integrated PMIC (buck/boost/LDOs) with embedded sequencer; 20-pin VQFN; fixed internal sequencing vs. capacitor-programmable delay. | Replaces discrete DC-DC + sequencer combo; targets compact portable designs; lacks UVSET monitoring and FAULT bus daisy-chain. | Choose TPS6508641RSLR for cost-sensitive, space-constrained apps needing integrated regulation; retain MAX16165ATPH+ for high-reliability, field-upgradable, multi-board sequencing. |
Compared with MAX16166ATPH+, MAX16165ATPH+ provides open-drain outputs essential for fault-bus arbitration and mixed-voltage domain interfacing, while TPS6508641RSLR trades configurability and scalability for integration density - making MAX16165ATPH+ optimal for modular, high-availability systems requiring deterministic, externally tunable sequencing.
Availability
MAX16165ATPH+ is available at Aetrix Electronics and suitable for FPGA/ASIC power sequencing, server PSU management, and industrial motor drive control requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for MAX16165ATPH+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, communications, and automotive markets.
The MAX16165ATPH+ belongs to Analog Devices' high-integrity power management sequencer family, engineered specifically for mission-critical multi-rail systems where deterministic startup, robust fault response, and seamless scalability are mandatory.
FAQ
What is the function of the IOS pin on the MAX16165ATPH+?
The IOS pin on the MAX16165ATPH+ sets the resistor-programmable offset current (0.5–50μA) injected into SET_ nodes during power-off sequencing. This ensures reliable detection of rail collapse by lowering the effective threshold, preventing false "rail-stuck-high" faults. The MAX16165ATPH+ uses this current to guarantee clean reverse-order shutdown even with lightly loaded or slow-discharge rails.
Does the MAX16165ATPH+ support daisy-chaining, and how is it implemented?
Yes, the MAX16165ATPH+ supports unlimited daisy-chaining via its bidirectional FAULT pin and ON input. When FAULT asserts low on one device, it pulls ON low on the next in chain, propagating fault or sequencing commands across multiple units. This enables synchronized control of dozens of power rails without additional logic - a capability confirmed in the MAX16165ATPH+ functional diagram and Applications Information section.
What is the difference between the FAULT response for UVSET undervoltage versus other fault conditions on the MAX16165ATPH+?
The MAX16165ATPH+ holds FAULT low continuously during UVSET undervoltage, but issues only an 80μs one-shot pulse for all other faults (e.g., SET_ timeout, external FAULT pull-down). This distinction allows host firmware to differentiate persistent supply failure from transient events. The MAX16165ATPH+ datasheet explicitly defines this dual-mode behavior in the Fault Input/Output and State Diagram sections.
Can the MAX16165ATPH+ sequence fewer than four channels, and how is it configured?
Yes, the MAX16165ATPH+ supports channel skipping: connect any unused SET_ pin (e.g., SET2) directly to ABP to disable that channel. During initialization, the MAX16165ATPH+ detects ABP-level voltage (>0.5V) and removes that channel from the sequencing state machine - eliminating delay, monitoring, and fault response for that rail. This is documented in the Skip or Disable Channels section of the MAX16165ATPH+ datasheet.
What package type and dimensions does the MAX16165ATPH+ use, and is thermal performance characterized?
The MAX16165ATPH+ uses a 20-bump Wafer-Level Package (WLP) measuring 1.63mm × 2.03mm with an exposed pad (EP) internally connected to GND. Its junction-to-ambient thermal resistance (θJA) is 55.49°C/W on a four-layer board, and EP must be soldered to the GND plane for effective heat dissipation - all values confirmed in the Package Information section of the official MAX16165ATPH+ datasheet.
MAX16165ATPH+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 4
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain, Open Drain
- Reset:
- Active Low
- Reset Timeout:
- 68µs Minimum
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TQFN (4x4)
MAX16165ATPH+ FAQ
1.How can I place an order for MAX16165ATPH+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX16165ATPH+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX16165ATPH+ reliable?
The price and inventory of MAX16165ATPH+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX16165ATPH+ is usually 5 days.
3.What payment methods are accepted for MAX16165ATPH+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX16165ATPH+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX16165ATPH+?
MAX16165ATPH+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX16165ATPH+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX16165ATPH+?
For technical support, including MAX16165ATPH+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX16165ATPH+ requirements.
6.How does Aetrix verify that MAX16165ATPH+ is sourced from the original manufacturer or authorized distributors?
All MAX16165ATPH+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX16165ATPH+ meets industry standards.
7.What is the process for return or replacement of MAX16165ATPH+?
All MAX16165ATPH+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX16165ATPH+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX16165ATPH+ part is unused and in its original packaging.
Return procedure for MAX16165ATPH+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX16165ATPH+ Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
