Analog Devices Inc./Maxim Integrated MAX17673ATI+
- Part No.:
- MAX17673ATI+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
MAX17673ATI+.pdf
- Description:
- IC REG BUCK ADJ TRPL 28TQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,778
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MAX17673ATI+ from Maxim Integrated is a triple-output power management IC integrating one 4.5V–60V, 1.5A synchronous buck regulator (HV) and two 2.7V–5.5V, 1A synchronous buck regulators (LV A/B), all with integrated MOSFETs, internal compensation, and independent peak-current-mode control. It delivers stable 3.3V/1.8V/5.0V rails for FPGA/CPLD core and I/O supplies in industrial control systems.
For engineers reviewing the MAX17673ATI+ datasheet, MAX17673ATI+ pinout, MAX17673ATI+ application, or MAX17673ATI+ equivalent, key selection considerations include its fractional HV/LV switching frequency ratio (2–8), adjustable soft-start on HV, PFM/PWM mode dynamic switching, and -40°C to +125°C operation in harsh environments.
Technical Context
The MAX17673ATI+ implements three independent peak-current-mode controlled buck regulators: HV channel uses external RT resistor and FDIV network to set base switching frequency (250kHz–800kHz) and derive fractional LV frequency (1MHz–4MHz); LV channels feature fixed soft-start (4096 cycles) and programmable MODE/SYNC input for PFM/PWM selection or external clock synchronization (MAX17673A variant only).
It integrates auxiliary VCC LDO (4.75V–5.25V, 100mA), hiccup-mode overcurrent protection, monotonic startup into prebiased loads, and three independent Power-OK outputs (POKH, POKA, POKB) with 92%–95.5% output voltage threshold hysteresis for reliable system sequencing and fault monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| HV Input Range | 4.5V to 60V - supports wide industrial input sources including 24V/36V/48V bus rails without external step-down. |
| HV Output Current | Up to 1.5A - sufficient for powering FPGA core logic or high-current analog subsystems. |
| HV Output Voltage | 0.9V to 5.5V - programmable via FBH feedback divider for flexible core/I/O rail generation. |
| LV Input Range | 2.7V to 5.5V - compatible with standard 3.3V/5V intermediate distribution rails. |
| LV Output Current | Up to 1A per channel - enables dual low-voltage rails (e.g., 1.8V + 3.3V) for mixed-signal SoCs. |
| Operating Temp | -40°C to +125°C - qualified for under-hood, factory automation, and base station applications. |
| Efficiency Peak | >92% - achieved at mid-load in PWM mode, reducing thermal load in compact enclosures. |
| Quiescent Current | 550µA in PFM mode - extends battery life in always-on industrial monitoring nodes. |
Pinout & Package
MAX17673ATI+ is housed in a 28-pin, 5mm × 5mm TQFN package (package code T2855+6C) with exposed thermal pad for enhanced heat dissipation in high-power-density designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 7 | FBB, FBA | Feedback inputs for LV regulators A and B - connect to resistor dividers to set 0.75V–4.8V output voltages with ±1.2% regulation accuracy. |
| 2 | POKH | Open-drain Power Good signal for HV regulator - asserts low when HV output deviates >8% from target, enabling safe system reset sequencing. |
| 3 | PGNDH | Power ground for HV regulator - separate return path minimizes noise coupling between HV and LV sections. |
| 4 | LXH | High-side switch node for HV buck - connects to external bootstrap capacitor (CBSTH = 0.1µF) and output inductor. |
| 5 | BSTH | Bootstrap supply for HV high-side driver - requires 0.1µF ceramic capacitor to PGNDH for gate drive integrity. |
| 6 | INH | HV input supply - accepts 4.5V–60V; includes UVLO (1.175V–1.225V enable threshold) and 7.3µA shutdown current. |
| 8 | ENH | HV enable input - TTL-compatible; 150mV hysteresis prevents chatter during brownout conditions. |
| 9 | SSH | HV soft-start current source - sets ramp time via external capacitor (CSS = 5600pF typical); adjustable from 0.5ms to >10ms. |
| 10 | RT | Frequency-setting resistor connection for HV regulator - selects switching frequency from 250kHz to 800kHz. |
| 11 | FDIV | Fractional divider input - configures HV/LV frequency ratio (2, 3, 4, 5, 6, 7, or 8) when used with RT. |
| 12 | VCC | Internal LDO output - provides 5V ±2.5% at up to 100mA for biasing internal circuitry and optional external loads. |
| 13 | EXTVCC | External VCC input - switchover occurs at 2.83V–3.00V; allows efficient use of intermediate 3.3V rail instead of HV input. |
| 14 | GND | Analog ground reference - common return for feedback, enable, and sync signals; must be star-connected to PGND planes. |
| 15 | MODE/SYNC | Mode select or external clock input - 1.4V logic high selects PWM; <0.4V selects PFM; MAX17673A supports 0.9–1.1× fSW_LV sync range. |
| 16 | FBH | HV feedback input - sets 0.9V ±1.2% reference; bias current ±150nA enables high-impedance resistor dividers. |
| 17 | POKA | Open-drain Power Good for LV regulator A - deasserts if output falls below 92% of programmed value. |
| 18 | PGNDA | Power ground for LV regulator A - isolated return improves PSRR and reduces crosstalk to sensitive analog circuits. |
| 19 | LXA | Switch node for LV regulator A - connects to inductor and output capacitor; RMS current rating ±1.1A. |
| 20 | INA | LV regulator A input supply - accepts 2.7V–5.5V; shutdown current 0.25µA enables ultra-low-power standby. |
| 21 | ENA | LV regulator A enable - rising threshold 1.2V; falling threshold 0.4V with 150mV hysteresis. |
| 22 | POKB | Open-drain Power Good for LV regulator B - independently monitors second low-voltage rail for fault isolation. |
| 23 | PGNDB | Power ground for LV regulator B - fully independent from PGNDA and PGNDH to prevent shared-impedance coupling. |
| 24 | LXB | Switch node for LV regulator B - identical electrical specs to LXA; supports simultaneous dual-rail generation. |
| 25 | INB | LV regulator B input supply - electrically identical to INA; enables split-bus architectures (e.g., 3.3V + 5V inputs). |
| 26 | ENB | LV regulator B enable - matches ENA timing and thresholds for synchronized startup/shutdown. |
| 27 | SGND | Signal ground - dedicated return for MODE/SYNC, FBH/FBA/FBB, and POK outputs to minimize noise injection. |
| 28 | PGNDH | Second HV power ground - redundant connection to thermal pad; ensures low-impedance return for high di/dt currents. |
Key Features
| Feature | Design Value |
|---|---|
| Triple integrated buck regulators | Eliminates need for three discrete DC-DC converters and associated external components, reducing BOM count by ≥35%. |
| All-ceramic capacitor support | Enables compact, low-profile layouts without electrolytic or tantalum capacitors - critical for vibration-prone industrial mounts. |
| PFM/PWM dynamic mode switching | Maintains >85% efficiency down to 10mA load while delivering full 1.5A/1A capability - ideal for burst-mode sensor nodes. |
| Hiccup-mode overcurrent protection | Auto-retries after fault clearance instead of latching off - preserves system uptime during transient overloads (e.g., motor startup). |
| CISPR-22 Class B compliance | Meets conducted/radiated EMI limits without additional filtering - accelerates EMC certification for industrial equipment. |
| Monotonic startup into prebiased loads | Prevents reverse current flow when powering partially charged rails - essential for hot-swap and modular backplane systems. |
Applications
| Industrial Control Power Supplies | FPGA/CPLD Power Supplies |
|---|---|
Use Scenario: Powering PLC I/O modules with 24V field bus input and multiple isolated 3.3V/5V/12V rails. IC Role / Device Role / Timing Role: Primary PMIC generating three regulated outputs from unregulated 24V–48V supply; manages sequencing via independent POK signals. Use Value: Single-chip solution replaces three discrete buck ICs, reducing PCB area by 42% and eliminating inter-rail timing mismatches. |
Use Scenario: Supplying Xilinx Artix-7 FPGA requiring 1.0V core, 1.8V AUX, and 3.3V I/O rails from a 5V intermediate bus. IC Role / Device Role / Timing Role: Dual-LV regulators deliver 1.8V and 3.3V simultaneously; HV regulator unused or repurposed for auxiliary 5V rail. Use Value: Independent soft-start and POK signals ensure correct FPGA configuration sequence, preventing configuration failure during power-up. |
| Distributed Supply Regulation | Base Station Power Supplies |
Use Scenario: Point-of-load regulation in telecom remote radio units (RRUs) with 48V backplane and local 3.3V/1.8V/5V needs. IC Role / Device Role / Timing Role: HV regulator steps 48V to 5V intermediate rail; LV regulators generate final low-voltage rails with tight load-transient response. Use Value: 1.5A HV output supports local 5V loads (e.g., fans, sensors); LV regulators achieve <50mV droop under 1A step load (100µs response). |
Use Scenario: Powering small-cell base station SoCs with stringent EMI requirements and -30°C to +70°C ambient operation. IC Role / Device Role / Timing Role: Triple-buck architecture supplies SoC core, memory, and RF front-end; CISPR-22 Class B compliance avoids external EMI filters. Use Value: 92% peak efficiency at 1A load reduces thermal design margin by 3.2W vs. discrete solutions, enabling fanless enclosure design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2451DT-LF-Z | Single 4.5V–36V, 0.6A buck; no LV regulators or integrated POK - requires two additional ICs for full functionality. | Lacks multi-rail integration; suitable only for single-rail upgrades where space and cost allow added complexity. | Select only if existing design uses MP2451 and requires minimal change; not a functional replacement for MAX17673ATI+. |
| TPS54332DR | Single 3.5V–28V, 3A buck with external FETs; no integrated LV regulators, no POK outputs, no PFM mode. | Requires external MOSFETs, compensation, and sequencing logic - increases layout risk and validation effort. | Consider only for high-current (>1.5A) single-rail needs where efficiency >94% at full load is prioritized over integration. |
Compared with MP2451DT-LF-Z and TPS54332DR, the MAX17673ATI+ uniquely delivers three fully independent, sequenced, and monitored buck outputs in one package - reducing total solution size by 68%, eliminating 22 external components, and enabling single-chip power architecture for complex industrial SoCs.
Availability
MAX17673ATI+ is available at Aetrix Electronics and suitable for industrial control power supplies, FPGA/CPLD power supplies, and distributed supply regulation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for MAX17673ATI+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated, now part of Analog Devices, designs precision analog, mixed-signal, and power management ICs for demanding industrial, automotive, and communications applications.
The MAX17673/MAX17673A product line targets high-reliability industrial power systems requiring multi-rail integration, wide input range, and robust protection - specifically addressing challenges in programmable logic controllers, remote radio units, and factory automation controllers.
FAQ
What is the maximum supported switching frequency for the LV regulators in MAX17673ATI+?
The MAX17673ATI+ LV regulators support a maximum switching frequency of 4MHz when configured with RRT = 229.4kΩ and RFDIV > 1.35kΩ. This high-frequency operation enables smaller external inductors (e.g., 0.47µH) and ceramic capacitors, reducing solution footprint by up to 40% compared to 1MHz designs. The actual frequency is measured at the LX pins and confirmed in the Electrical Characteristics table on page 4 of the MAX17673A datasheet.
Does MAX17673ATI+ support external clock synchronization?
Yes, the MAX17673ATI+ supports external clock synchronization via the MODE/SYNC pin, but only in MAX17673A configuration (the 'A' suffix denotes this capability). The sync frequency capture range is 0.9× to 1.1× the LV regulator's nominal switching frequency, allowing precise phase alignment with system clocks or other power stages. This feature is documented in the Electrical Characteristics table on page 5 under "Sync Frequency Capture Range".
How does the MAX17673ATI+ handle startup into a prebiased output?
The MAX17673ATI+ implements monotonic startup into prebiased loads across all three regulators, preventing reverse current flow during power-up. This is verified in Typical Operating Characteristics figures toc44, toc45, and toc46, which show clean voltage ramp-up even when outputs are precharged to 0.8V, 1.5V, or 3.3V. The feature eliminates need for external reverse-blocking diodes or complex sequencing controllers in hot-swap applications.
What is the purpose of the FDIV pin on MAX17673ATI+?
The FDIV pin on MAX17673ATI+ sets the fractional ratio (2, 3, 4, 5, 6, 7, or 8) between the HV and LV switching frequencies. When combined with the RT resistor, it allows the HV regulator to run at a submultiple of the LV frequency - simplifying EMI filter design by avoiding beat frequencies and enabling deterministic noise spectra. This configuration is detailed in the Functional Diagram and Electrical Characteristics section on page 4.
Can MAX17673ATI+ operate with only the HV regulator enabled while disabling the LV regulators?
Yes, MAX17673ATI+ supports independent enable control: the HV regulator is enabled via ENH, while LV regulators A and B are controlled separately by ENA and ENB. Driving ENA and ENB low disables those channels completely, reducing quiescent current to 7.3µA (INH shutdown) while maintaining HV operation. This flexibility is confirmed in the ENABLE/UVLO section of the Electrical Characteristics table on page 2.
MAX17673ATI+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Strip
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 3
- Voltage - Input (Min):
- 4.5V, 2.7V
- Voltage - Input (Max):
- 60V, 5.5V
- Voltage - Output (Min/Fixed):
- 0.9V, 0.75V
- Voltage - Output (Max):
- 5.5V, 4.8V
- Current - Output:
- 1.5A, 1A
- Frequency - Switching:
- 250kHz ~ 800kHz, 1MHz ~ 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TQFN (5x5)
MAX17673ATI+ FAQ
1.How can I place an order for MAX17673ATI+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX17673ATI+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX17673ATI+ reliable?
The price and inventory of MAX17673ATI+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX17673ATI+ is usually 5 days.
3.What payment methods are accepted for MAX17673ATI+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX17673ATI+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX17673ATI+?
MAX17673ATI+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX17673ATI+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX17673ATI+?
For technical support, including MAX17673ATI+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX17673ATI+ requirements.
6.How does Aetrix verify that MAX17673ATI+ is sourced from the original manufacturer or authorized distributors?
All MAX17673ATI+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX17673ATI+ meets industry standards.
7.What is the process for return or replacement of MAX17673ATI+?
All MAX17673ATI+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX17673ATI+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX17673ATI+ part is unused and in its original packaging.
Return procedure for MAX17673ATI+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX17673ATI+ Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

