Analog Devices Inc./Maxim Integrated MAX191ACWG+

Overview

The MAX191ACWG+ from Maxim Integrated is a monolithic, CMOS 12-bit successive-approximation analog-to-digital converter (ADC) with differential pseudo-differential inputs, integrated track/hold, internal 4.096V reference with REFADJ trim input, and dual serial/parallel µP interface. It delivers 100ksps guaranteed sample rate, 7.5µs conversion time, and operates from single +5V or dual ±5V supplies - enabling ground-referenced bipolar signal acquisition in portable data loggers and industrial process controllers.

For engineers reviewing the MAX191ACWG+ datasheet, MAX191ACWG+ pinout, MAX191ACWG+ application, or MAX191ACWG+ equivalent, this page provides verified technical context, package-specific pin functions, real-world interface timing constraints, and validated alternative options for low-power, high-accuracy sampling systems requiring internal reference stability and power-down capability.

Technical Context

The MAX191ACWG+ implements a SAR architecture with on-chip track/hold and internal bandgap voltage reference (4.096V ±20mV at +25°C, 80ppm/°C tempco). Its analog front-end supports pseudo-differential operation: AIN+ is actively sampled while AIN− serves as stable return reference, requiring ≤±0.1LSB drift during conversion.

Digital interface flexibility includes three modes: slow-memory parallel (two 8-bit reads), ROM-mode parallel (three-read sequence), and SPI/MICROWIRE/QSPI-compatible serial mode using SCLK, SSTRB, and SCLKOUT. Clocking supports either external 100kHz–1.6MHz TTL/CMOS source or internal oscillator with 120pF capacitor (≈1MHz nominal).

Key Specifications

Pinout & Package

MAX191ACWG+ is supplied in a 24-pin wide SO (SOIC-W) package, 7.5mm body width, 1.27mm pitch, RoHS-compliant. Pin 1 marked with dot; pin numbering follows standard SOIC convention (counterclockwise from top-left corner).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 12-bit sampling ADC applications.

Compared with ADS7816U and MAX11131AUT+, the MAX191ACWG+ uniquely combines internal 4.096V reference with REFADJ trim, dual-supply bipolar operation, and parallel/serial interface flexibility - making it optimal for industrial data acquisition where calibration stability, signal range, and µP compatibility are jointly critical.

Availability

MAX191ACWG+ is available at Aetrix Electronics and suitable for battery-powered data loggers, PC pen digitizers, and high-accuracy process control systems requiring stable component supply, long-term lifecycle continuity, and traceable sourcing.

Supply support for MAX191ACWG+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power-management ICs for industrial, medical, and communications applications.

The MAX191 belongs to Maxim's legacy high-accuracy data acquisition product line, engineered specifically for low-power, high-stability sampling in portable and embedded instrumentation where internal reference integrity and flexible µP interfacing are essential.

FAQ

What supply configurations does the MAX191ACWG+ support?

The MAX191ACWG+ operates from either a single +5V ±5% supply (VDD = +5V, VSS = 0V) or dual supplies (VDD = +5V, VSS = –5V ±5%). Dual-supply operation enables true bipolar input ranges (±4.096V), while single-supply supports unipolar 0–4.096V acquisition. AGND and DGND must be connected at a single point near the device to minimize noise coupling. The MAX191ACWG+ draws 3mA typical in active mode and drops to 50µA max when PD is pulled low.

How does the REFADJ pin function in the MAX191ACWG+?

The REFADJ pin on the MAX191ACWG+ provides a trim input for the internal 4.096V reference, allowing system-level gain calibration. With a nominal voltage of 2.4V, adjusting REFADJ by ±0.5V changes VREF by approximately ±0.87V (1.7× gain factor), correcting for system-level gain errors. When REFADJ is tied to VDD, the MAX191ACWG+ accepts an external reference at the VREF pin. This dual-mode capability eliminates the need for external DACs or potentiometers in precision calibration workflows.

What are the timing requirements for initiating a conversion in parallel mode on the MAX191ACWG+?

In parallel slow-memory mode, the MAX191ACWG+ starts conversion on the simultaneous falling edge of CS, RD, and HBEN (all low). BUSY goes low immediately, and the 7.5µs conversion completes with BUSY returning high. The first read accesses the 8 LSBs on D7–D0; a second read with HBEN high retrieves the 4 MSBs. Critical timing constraints include t_{CS–RD setup} ≥ 0ns and t_{RD pulse width} ≥ 150ns (CL = 100pF). Violating synchronization with CLK edges within 50ns before or 100ns after causes measurable offset/feedthrough errors.

Can the MAX191ACWG+ interface directly with SPI microcontrollers?

Yes, the MAX191ACWG+ supports SPI, QSPI, and MICROWIRE protocols in serial mode (PAR = low). It uses CS as frame sync, SCLK as clock input, SCLKOUT as derived clock output, SSTRB as data-valid strobe, and DOUT as MSB-first serial data output. No level-shifting or protocol translation is required for standard 3.3V or 5V SPI masters. The MAX191ACWG+ does not require MISO/MOSI bidirectional lines - its serial interface is strictly master-out/slave-in with dedicated SCLKOUT and SSTRB outputs for precise timing alignment.

What is the significance of pseudo-differential input in the MAX191ACWG+?

The MAX191ACWG+ employs a pseudo-differential input architecture: only AIN+ is actively sampled by the internal track/hold, while AIN− serves as a stable reference return. For accurate results, AIN− must remain within ±0.1LSB (≈0.5mV) of AGND during conversion - achieved by bypassing AIN− to AGND with a 0.1µF capacitor. This structure allows bipolar signal acquisition without full differential front-end complexity, supporting both single-ended sensors (AIN− = AGND) and transformer-coupled inputs (AIN− referenced to center tap).