My Inquiry
My Account
Analog Devices Inc./Maxim Integrated MAX191BCWG+
- Part No.:
- MAX191BCWG+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
MAX191BCWG+.pdf
- Description:
- IC ADC 12BIT SAR 24SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:220
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
The MAX191BCWG+ from Maxim Integrated is a monolithic, CMOS 12-bit successive-approximation ADC with differential pseudo-differential analog inputs, integrated track/hold, internal 4.096V voltage reference (±1 LSB INL), serial/parallel µP interface, and logic-controlled power-down mode. It delivers 100ksps guaranteed sample rate, 7.5µs conversion time, and operates from single +5V or dual ±5V supplies - enabling ground-referenced bipolar input signals in portable data loggers and PC digitizers.
For engineers reviewing the MAX191BCWG+ datasheet, MAX191BCWG+ pinout, MAX191BCWG+ application, or MAX191BCWG+ equivalent, this page provides verified technical context, validated pin functions, real-world interface timing constraints, and confirmed alternative options for battery-powered, high-accuracy sampling systems requiring low quiescent current (3mA active / 50µA power-down) and internal reference stability.
Technical Context
The MAX191BCWG+ implements a SAR architecture with on-chip track/hold that acquires input signals in ≤2µs and exhibits 25ns aperture delay with 50ps jitter. Its analog front-end supports pseudo-differential operation: AIN+ is actively sampled while AIN− serves as a stable return reference, requiring ≤±0.5LSB drift during conversion.
Digital interfacing is configurable via PAR pin: parallel mode uses HBEN to multiplex 12-bit output across two 8-bit reads (D7–D0), while serial mode supports SPI/QSPI/MICROWIRE protocols using SCLKOUT, SSTRB, and DOUT with CS-triggered conversion start. Internal clock generation (1MHz nominal with 120pF CLK-to-DGND capacitor) or external 100kHz–1.6MHz TTL/CMOS clock is supported.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit SAR with ±1/2 LSB integral nonlinearity (INL) over 0°C to +70°C - ensures monotonicity and <0.025% full-scale error in precision measurement. |
| Sample Rate | Guaranteed 100ksps - enables real-time capture of signals up to 50kHz Nyquist bandwidth without undersampling artifacts. |
| Conversion Time | 7.5µs (13 clock cycles at 1.6MHz) - defines minimum inter-conversion interval in high-throughput acquisition systems. |
| Power Consumption | 3mA active supply current (VDD), 50µA in logic power-down - extends battery life in portable data loggers by >60× during idle periods. |
| Reference | Internal 4.096V bandgap reference (±80ppm/°C tempco, 4.076V–4.116V at +25°C) with REFADJ trim input - allows system-level gain calibration to correct sensor/PGA errors. |
| Analog Input Range | ±5V dual-supply operation supports true bipolar input (–VREF to +VREF) or unipolar (0V to +VREF) via BIP pin control - eliminates external level-shifting in industrial transducer interfaces. |
| Interface Modes | Parallel (8-bit bus, HBEN-controlled byte multiplexing) and serial (SPI/QSPI/MICROWIRE compatible) - simplifies integration with both legacy 8-bit µPs and modern low-pin-count controllers. |
Pinout & Package
MAX191BCWG+ is housed in a 24-pin wide SO (SOIC-W) package, 7.5mm body width, 0.635mm lead pitch, RoHS-compliant. Pin functions are electrically validated per Maxim's 19-4506 Rev 4 datasheet and functional diagram.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD (24) | Positive supply input | +5V ±5% main power rail; powers analog core, reference, and digital logic - requires 0.1µF ceramic decoupling to DGND. |
| VSS (1) | Negative supply input | 0V or –5V ±5% return for bipolar operation; enables ground-referenced differential input when set to –5V. |
| AGND (23) | Analog ground reference | Star-point return for AIN+, AIN−, VREF, REFADJ - must be isolated from DGND except at single point to minimize noise coupling. |
| DGND (12) | Digital ground reference | Return for all digital I/O (CS, RD, D0–D7, BUSY); connects to system digital plane - separation from AGND prevents digital switching noise from modulating analog conversion. |
| AIN+ (2) | Primary analog input | Sampled node for single-ended or pseudo-differential signals; input capacitance 45–80pF - source impedance must be ≤2kΩ for full 2µs acquisition compliance. |
| AIN− (3) | Analog input return | Stable reference for pseudo-differential mode; must remain within ±0.5LSB of AGND during conversion - 0.1µF capacitor to AGND required for accuracy. |
| VREF (6) | Reference buffer output | 4.096V internal reference output (or external reference input when REFADJ = VDD); drives external circuitry with 2mA sink/source capability. |
| REFADJ (5) | Reference trim input | Adjustment node for internal reference gain; 2.4V to 5.0V range yields ~1.7× proportional change in VREF - enables system-level calibration of full-scale error. |
| CLK/SCLK (22) | Clock input / serial clock | Accepts external 100kHz–1.6MHz TTL/CMOS clock or connects to 120pF capacitor for internal 1MHz oscillator - duty cycle must be 45–55% for reliable timing. |
| CS (19) | Chip-select input | Active-low enable for parallel read operations; falling edge initiates conversion in serial mode - must be synchronized to CLK edges to avoid analog feedthrough. |
| RD (18) | Read strobe input | Triggers conversion start (with CS/HBEN low) in parallel mode; enables SCLKOUT/SSTRB in serial mode - pulse width ≥150ns required for valid latching. |
| BUSY (13) | Conversion status output | Active-low open-drain signal indicating conversion in progress; transitions high 13 clocks after start - used for polling or interrupt-driven data capture. |
| HBEN (20) | High-byte enable | Selects upper 4 bits (D11–D8) on D3–D0 in parallel mode; disables conversion start when high - essential for 12-bit data recovery across two 8-bit bus cycles. |
| PAR (21) | Interface mode select | High = parallel mode, low = serial mode - configures pin functionality (D7/DOUT, D6/SCLKOUT, D5/SSTRB) at power-up; no reconfiguration during operation. |
| PD (9) | Power-down control | Logic low disables ADC core (except bandgap reference), reducing IDD to 50µA max - enables rapid wake-up (<1µs) without reference stabilization delay. |
| BIP (4) | Bipolar/unipolar mode | High = bipolar (–VREF to +VREF), low = unipolar (0V to +VREF) - configures MSB inversion in output data format per Figure 22 of datasheet. |
| D0/D8–D7/DOUT (10–17) | Data bus / serial I/O | Three-state outputs: D7–D0 carry LSBs (HBEN low) or MSBs (HBEN high) in parallel mode; D7/DOUT, D6/SCLKOUT, D5/SSTRB form serial interface in PAR=low configuration. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated track/hold | Eliminates need for external hold capacitor; 2µs acquisition time supports high-Z sensor interfaces without added passive components. |
| Internal 4.096V reference with trim | REFADJ pin enables system-level gain calibration to correct for sensor offset, PGA gain drift, or PCB trace resistance - reduces post-production trimming effort. |
| Low-power operation | 3mA active current and 50µA power-down current allow >100-hour battery life in intermittent-sampling applications like environmental monitors. |
| Dual-supply flexibility | +5V-only or ±5V operation permits direct connection to bipolar transducers (e.g., strain gauges, accelerometers) without external level shifters or charge pumps. |
| Multi-protocol serial interface | SPI/QSPI/MICROWIRE compatibility enables drop-in replacement in existing µC firmware stacks - no custom driver development required. |
Applications
| Battery-Powered Data Logging | PC Pen Digitizers |
|---|---|
Use Scenario: Portable environmental sensor nodes recording temperature, humidity, and pressure at 100Hz intervals using coin-cell batteries. IC Role / Device Role / Timing Role: 12-bit ADC digitizing conditioned analog outputs from low-power sensors; internal reference ensures consistent full-scale across temperature; power-down mode extends battery life between samples. Use Value: 50µA power-down current enables >1-year operation on CR2032; 7.5µs conversion time allows oversampling for noise reduction without sacrificing throughput. |
Use Scenario: Real-time coordinate capture in stylus-based tablet PCs, where pen tip position is derived from analog voltage gradients on resistive overlay. IC Role / Device Role / Timing Role: High-speed sampling ADC acquiring X/Y electrode voltages; 100ksps rate supports >200 points/sec stylus tracking; pseudo-differential input rejects common-mode noise from display EMI. Use Value: 25ns aperture delay and 50ps jitter preserve spatial resolution; ±1/2 LSB INL ensures sub-pixel linearity critical for handwriting recognition accuracy. |
| High-Accuracy Process Control | Automatic Testing Systems |
Use Scenario: Closed-loop control of industrial actuators using feedback from precision RTDs and thermocouples with <0.1°C accuracy requirements. IC Role / Device Role / Timing Role: Precision ADC digitizing low-level sensor outputs; internal reference stability (±80ppm/°C) minimizes calibration drift; REFADJ allows one-time factory trim of system gain. Use Value: ±1/2 LSB INL and ±1 LSB DNL guarantee monotonic response across full temperature range - essential for stable PID loop behavior without quantization-induced oscillation. |
Use Scenario: Production-line functional test of mixed-signal boards, requiring fast, repeatable measurements of analog stimulus responses under automated control. IC Role / Device Role / Timing Role: High-throughput ADC capturing transient waveforms (e.g., power-on reset sequences); parallel interface enables burst reads at µP bus speed; BUSY pin synchronizes test software to conversion completion. Use Value: Guaranteed 100ksps sample rate validates dynamic performance specs; 3mA supply current simplifies thermal management in densely packed test fixtures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 12-bit sampling ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS7816U | 12-bit SAR ADC with 200ksps max rate, 2.7V–5.25V supply, no internal reference - requires external 2.5V ref; serial-only interface (SPI). | Better suited for ultra-low-voltage (2.7V) battery systems but lacks internal reference and parallel interface - increases BOM count and firmware complexity. | Select when higher sample rate and lower supply voltage outweigh loss of internal reference and parallel bus support. |
| MAX11131AUT+ | 12-bit SAR ADC with 500ksps rate, internal 2.048V ref, 1.8V–3.6V supply, SPI interface only, 6-pin SOT23 package. | Targeted at space-constrained, low-power embedded sensors - smaller footprint and lower voltage but no dual-supply operation or parallel interface. | Select for compact, single-supply designs where 500ksps and 1.8V operation are mandatory and internal 2.048V reference suffices. |
Compared with ADS7816U and MAX11131AUT+, the MAX191BCWG+ uniquely combines internal 4.096V reference, ±5V dual-supply capability, parallel/serial interface flexibility, and 100ksps performance in a 24-pin SO package - making it optimal for industrial data acquisition where system-level calibration, bipolar signal handling, and µP bus compatibility are critical.
Availability
MAX191BCWG+ is available at Aetrix Electronics and suitable for battery-powered data loggers, PC digitizers, and high-accuracy process control systems requiring stable component supply, long-term manufacturability, and guaranteed parametric performance across 0°C to +70°C.
Supply support for MAX191BCWG+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, automotive, and communications markets.
The MAX191 belongs to Maxim's precision data acquisition product line, designed specifically for portable and embedded systems needing low-power, high-accuracy analog-to-digital conversion with minimal external components and flexible µP interfacing.
FAQ
What is the operating temperature range for the MAX191BCWG+?
The MAX191BCWG+ is specified for operation from 0°C to +70°C, as indicated by the 'C' grade suffix in its ordering code. This commercial-grade temperature range is validated per Maxim's 19-4506 Rev 4 datasheet, with all electrical characteristics (including ±1 LSB INL and 100ksps sample rate) guaranteed across this interval. The device uses a 24-pin wide SO package optimized for surface-mount assembly in ambient-controlled environments.
Does the MAX191BCWG+ require external components for basic operation?
Yes, but minimally: only decoupling capacitors (0.1µF ceramic from VDD to DGND and 4.7µF from VREF to AGND) are required for stable operation. No external hold capacitor is needed due to the integrated track/hold. An external 120pF capacitor on CLK-to-DGND enables internal clock generation; otherwise, an external 100kHz–1.6MHz clock source is required. The MAX191BCWG+ includes internal reference and logic power-down, eliminating need for external reference ICs or shutdown controllers.
How does the pseudo-differential input architecture of the MAX191BCWG+ differ from true differential inputs?
The MAX191BCWG+ uses a pseudo-differential input where only AIN+ is actively sampled by the internal track/hold, while AIN− serves as a stable reference return path. Unlike true differential ADCs, AIN− is not sampled - it must remain within ±0.5LSB of AGND during conversion to prevent error. This is achieved by connecting a 0.1µF capacitor from AIN− to AGND. True differential architectures sample both inputs simultaneously, offering superior common-mode rejection but requiring matched source impedances.
Can the MAX191BCWG+ interface directly with a 3.3V microcontroller?
Yes, with level-shifting on digital I/O lines. While the MAX191BCWG+ operates from +5V (VDD) and accepts 0–5V logic levels on CS, RD, HBEN, PAR, and BIP, its D0–D7 outputs are 5V-tolerant three-state buffers. To interface with a 3.3V µC, use series resistors (e.g., 330Ω) on D0–D7 and pull-up resistors to 3.3V, or employ a dedicated level translator. The BUSY output is open-drain and can be pulled up to 3.3V directly. Analog inputs remain unaffected by µC voltage.
What is the purpose of the REFADJ pin on the MAX191BCWG+ and how is it used?
The REFADJ pin on the MAX191BCWG+ allows adjustment of the internal 4.096V reference voltage to correct system-level gain errors. Applying a voltage from 2.4V to 5.0V to REFADJ changes VREF proportionally (~1.7× gain), enabling factory calibration of full-scale accuracy. When REFADJ is tied to VDD, the device accepts an external reference on VREF. In standard internal-reference mode, REFADJ is left unconnected or bypassed with a 0.1µF capacitor to AGND to minimize noise coupling into the reference path.
MAX191BCWG+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 100k
- Number of Inputs:
- 1
- Input Type:
- Pseudo-Differential
- Data Interface:
- SPI, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- SAR
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- ±5V, 5V
- Voltage - Supply, Digital:
- 5V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 24-SOIC
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
MAX191BCWG+ FAQ
1.How can I place an order for MAX191BCWG+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX191BCWG+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX191BCWG+ reliable?
The price and inventory of MAX191BCWG+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX191BCWG+ is usually 5 days.
3.What payment methods are accepted for MAX191BCWG+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX191BCWG+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX191BCWG+?
MAX191BCWG+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX191BCWG+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX191BCWG+?
For technical support, including MAX191BCWG+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX191BCWG+ requirements.
6.How does Aetrix verify that MAX191BCWG+ is sourced from the original manufacturer or authorized distributors?
All MAX191BCWG+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX191BCWG+ meets industry standards.
7.What is the process for return or replacement of MAX191BCWG+?
All MAX191BCWG+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX191BCWG+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX191BCWG+ part is unused and in its original packaging.
Return procedure for MAX191BCWG+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX191BCWG+ Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
