Analog Devices Inc./Maxim Integrated MAX20057ATIA/VY+T
- Part No.:
- MAX20057ATIA/VY+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
MAX20057ATIA/VY+T.pdf
- Description:
- IC REG BOOST ADJ 3.5A DL 28TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MAX20057ATIA/VY+T from Analog Devices is an automotive-grade triple-output power management IC integrating two synchronous buck converters (3.5A/2A) and a 36V asynchronous boost controller, operating from 3.5V–36V input with cold-crank support down to 2V battery voltage. It delivers fixed 5V/3.3V outputs or adjustable 1V–14V outputs, features 2.1MHz/400kHz selectable switching frequency, and supports phase-shifted 180° interleaving for reduced input ripple - deployed in instrument clusters and start-stop systems.
For engineers reviewing the MAX20057ATIA/VY+T datasheet, MAX20057ATIA/VY+T pinout, MAX20057ATIA/VY+T application, or MAX20057ATIA/VY+T equivalent, key selection considerations include cold-crank regulation capability, spread-spectrum EMI reduction, FSYNC-synchronized multi-rail timing, thermal shutdown at 170°C, and thermally enhanced 5mm × 5mm TQFN-EP package with exposed pad.
Technical Context
The MAX20057ATIA/VY+T implements valley-current-mode control for both buck converters, enabling stable operation across wide VIN ranges including automotive transients. Its dual-buck architecture operates 180° out-of-phase with independent enable pins (EN1/EN2), while the boost controller uses external N-MOSFET drive via DL output and CSP-based cycle-by-cycle current limiting with 50mV threshold.
FSYNC enables three operational modes: forced PWM (fixed-frequency), skip mode (ultra-low IQ), and PLL-synchronized tracking to external clock; spread spectrum (±6% modulation) is factory-configured and disabled during external sync. Thermal protection triggers shutdown at 170°C with 20°C hysteresis, and undervoltage lockout for BIAS (3.1V rising / 2.6V falling) and boost SUP (4.5V rising) ensures robust startup sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.5V to 36V continuous; supports cold-crank operation down to 2.05V with boost pre-regulation |
| Buck1 Output Current | Up to 3.5A continuous; high-side RON = 50mΩ, low-side RON = 45mΩ at VBIAS = 5V |
| Buck2 Output Current | Up to 2A continuous; high-side RON = 100mΩ, low-side RON = 90mΩ at VBIAS = 5V |
| Switching Frequency | Factory-set 2.1MHz or 400kHz; ±6% spread spectrum enabled; FSYNC synchronizable with 1.8–2.6MHz or 250–550kHz range |
| Minimum On-Time | 20ns (buck), 60ns (boost); enables stable 3.3V output regulation at 2.1MHz without skip-mode jitter |
| Thermal Protection | 170°C junction shutdown with 20°C hysteresis; θJA = 27°C/W on four-layer board |
| Quiescent Current | 30μA typical with all regulators active; 1μA in full standby (all EN_ = low) |
Pinout & Package
Package: 28-pin TQFN-EP (5mm × 5mm), thermally enhanced with exposed pad connected to AGND/PGND for optimal heat dissipation (θJC = 3°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1, EN2, EN3 | Independent digital enable inputs | High-voltage tolerant (to 40V); control Buck1, Buck2, and Boost independently for precise power sequencing |
| FB1, FB2, FB3 | Feedback voltage sense inputs | Regulated to 1.0V (typ); support fixed-output (connect to BIAS) or adjustable 1V–14V via resistor divider |
| LX1, LX2 | Buck switch node outputs | Drive external inductors; require ceramic bootstrap capacitors between BST1/LX1 and BST2/LX2 |
| DL | Boost low-side gate driver output | Sources/sinks up to 1.67A peak; drives external N-MOSFET with logic-level compatibility when powered by BIAS |
| PGOOD1, PGOOD2 | Open-drain power-good indicators | Assert low if output drops below 93.5% of nominal; high-impedance above 95%; debounced (20μs) |
| FSYNC | External clock synchronization input | Accepts 250kHz–2.6MHz signal; controls mode (skip/FPWM), phase alignment (50% duty → 180° buck phase shift), and PLL lock |
Key Features
| Feature | Design Value |
|---|---|
| Cold-crank regulation | Maintains buck output regulation during automotive battery dips to 2.05V using integrated boost pre-regulator |
| EMI-optimized switching | 2.1MHz operation + 20ns min-on-time + spread spectrum (±6%) eliminates AM-band interference without filtering trade-offs |
| Interleaved buck architecture | 180° phase shift between Buck1/Buck2 reduces input capacitor RMS current and eases EMI filter design |
| Low-quiescent-power sequencing | 30μA total supply current with all rails active; 1μA deep standby enables always-on automotive modules |
| Robust protection suite | Cycle-by-cycle current limit, hiccup-mode short-circuit recovery, thermal shutdown (170°C), and UVLO on BIAS/SUP rails |
Applications
| Instrument Cluster Power Supply | Start-Stop System DC-DC Stage |
|---|---|
Use Scenario: Centralized power delivery for LCD display, microcontroller, CAN transceivers, and backlight drivers in vehicle dashboards. IC Role / Device Role / Timing Role: Triple-output PMIC providing isolated 5V (MCU core), 3.3V (peripherals), and 10V (backlight boost) with synchronized soft-start and rail sequencing. Use Value: Eliminates need for discrete buck/boost stages; 180° interleaving cuts input ripple by >70%, reducing bulk capacitance size and cost. | Use Scenario: Maintaining stable 5V/3.3V rails during engine cranking events where battery voltage collapses to 2–6V. IC Role / Device Role / Timing Role: Pre-boost controller sustains buck input above dropout during cold-crank; FSYNC locks all rails to master clock for deterministic transient response. Use Value: Guarantees uninterrupted operation of safety-critical ECUs without brownouts; 2.1MHz switching enables compact 2.2μH inductors. |
| Navigation Head Unit Power Management | Distributed Automotive Domain Controller |
Use Scenario: Powering GPS module, audio codec, touch controller, and RF front-end in infotainment head units. IC Role / Device Role / Timing Role: Dual-buck + boost topology supplies 5V (processor), 3.3V (sensors/I/O), and 10V (RF amplifier bias) with independent enable/control. Use Value: Spread-spectrum mode suppresses conducted EMI into sensitive RF bands; PGOOD signals coordinate subsystem wake-up timing. | Use Scenario: Consolidating power for ADAS domain controller submodules (camera ISP, radar MCU, Ethernet PHY). IC Role / Device Role / Timing Role: High-efficiency PMIC delivering 3.5A/2A rails with thermal-aware load shedding via EN_ pin control and temperature-triggered hiccup mode. Use Value: Thermally enhanced TQFN-EP package sustains 125°C ambient; 95% max duty cycle prevents dropout during 12V-to-5V conversion at low input. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX20090ATPA/VY+ | Single 3.5A buck + boost; no second buck channel; 2.2MHz fixed frequency only; no FSYNC or spread spectrum | Lacks interleaved dual-buck capability and rail sequencing flexibility; suited for simpler single-rail systems | Select when only one high-current rail is needed and EMI requirements are less stringent |
| TPS65321C-Q1 | Triple buck (3A/2A/1.5A) + LDO; no boost; 2.2MHz max; no cold-crank boost support; different pinout and control interface | Cannot regulate through 2V battery dips; requires external boost for cold-crank; lower integration for high-voltage pre-regulation | Select when boost functionality is unnecessary and system relies on upstream 12V stabilization |
Compared with MAX20090ATPA/VY+ and TPS65321C-Q1, the MAX20057ATIA/VY+T uniquely combines cold-crank-capable boost pre-regulation, dual interleaved bucks with independent enables, and FSYNC-synchronized spread-spectrum operation - making it the only option supporting full rail integrity during automotive transients without external circuitry.
Availability
MAX20057ATIA/VY+T is available at Aetrix Electronics and suitable for automotive start-stop systems, instrument clusters, and distributed DC power systems requiring stable component supply across extended temperature (-40°C to +125°C) and AEC-Q100 Grade 0 qualification.
Supply support for MAX20057ATIA/VY+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving automotive, industrial, and communications markets with AEC-Q100-qualified solutions.
The MAX20057ATIA/VY+T belongs to Analog Devices' automotive PMIC portfolio, engineered specifically for mid-to-high-power infotainment and body-control modules needing wide-input regulation, cold-crank resilience, and EMI-compliant switching in space-constrained layouts.
FAQ
What is the cold-crank input voltage limit supported by the MAX20057ATIA/VY+T?
The MAX20057ATIA/VY+T maintains regulated buck outputs during automotive cold-crank events down to 2.05V battery input, enabled by its integrated 36V asynchronous boost controller that pre-regulates the buck inputs. This capability is verified per AEC-Q100 transient test profiles and allows uninterrupted operation of safety-critical ECUs without brownout resets.
Does the MAX20057ATIA/VY+T support external clock synchronization, and what are the valid frequency ranges?
Yes, the MAX20057ATIA/VY+T supports external clock synchronization via the FSYNC pin. For 2.1MHz internal operation, FSYNC accepts 1.8MHz–2.6MHz signals; for 400kHz operation, it accepts 250kHz–550kHz. The device uses a PLL to lock internal clocks to the external signal, enabling deterministic phase alignment (e.g., 50% duty cycle yields 180° buck phase shift) and EMI reduction through frequency dithering.
How does the MAX20057ATIA/VY+T achieve ultra-low quiescent current in standby mode?
The MAX20057ATIA/VY+T achieves 1μA typical supply current in full standby (all EN_ = low) by disabling all switching regulators and bias circuitry, retaining only essential monitoring functions. With only Buck1 active (5V output), it draws 10μA; with Buck2 active (3.3V), 8μA; and with all three regulators active, 30μA - meeting stringent OEM requirements for always-on automotive modules.
What thermal protection mechanisms are implemented in the MAX20057ATIA/VY+T?
The MAX20057ATIA/VY+T incorporates thermal shutdown at 170°C junction temperature with 20°C hysteresis, plus cycle-by-cycle current limiting and hiccup-mode recovery for overcurrent faults. Its thermally enhanced 5mm × 5mm TQFN-EP package delivers θJA = 27°C/W on a four-layer board and θJC = 3°C/W, enabling reliable operation in under-hood environments up to +125°C ambient.
Can the MAX20057ATIA/VY+T generate a 10V output, and how is it configured?
Yes, the MAX20057ATIA/VY+T's boost controller provides a factory-configured 10V fixed output (VOUT3 = 9.75V–10.2V). To configure it, connect FB3 directly to the boost output (no resistor divider); the internal reference regulates FB3 to 1.005V (typ). For adjustable outputs, use an external resistive divider from boost output to FB3 and FB3 to AGND - enabling outputs from 1V to 36V depending on resistor ratio.
MAX20057ATIA/VY+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive
- Topology:
- Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2V
- Voltage - Input (Max):
- 40V
- Voltage - Output (Min/Fixed):
- 1V
- Voltage - Output (Max):
- 14V
- Current - Output:
- 3.5A
- Frequency - Switching:
- 2.1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 28-TQFN (5x5)
MAX20057ATIA/VY+T FAQ
1.How can I place an order for MAX20057ATIA/VY+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX20057ATIA/VY+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX20057ATIA/VY+T reliable?
The price and inventory of MAX20057ATIA/VY+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX20057ATIA/VY+T is usually 5 days.
3.What payment methods are accepted for MAX20057ATIA/VY+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX20057ATIA/VY+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX20057ATIA/VY+T?
MAX20057ATIA/VY+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX20057ATIA/VY+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX20057ATIA/VY+T?
For technical support, including MAX20057ATIA/VY+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX20057ATIA/VY+T requirements.
6.How does Aetrix verify that MAX20057ATIA/VY+T is sourced from the original manufacturer or authorized distributors?
All MAX20057ATIA/VY+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX20057ATIA/VY+T meets industry standards.
7.What is the process for return or replacement of MAX20057ATIA/VY+T?
All MAX20057ATIA/VY+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX20057ATIA/VY+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX20057ATIA/VY+T part is unused and in its original packaging.
Return procedure for MAX20057ATIA/VY+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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