Analog Devices Inc./Maxim Integrated MAX4928BETN+T

Overview

MAX4928BETN+T from Maxim Integrated is a high-speed passive 6×DPDT analog switch designed for routing PCIe Gen I/II and DisplayPort differential signals between GMCH and either PCIe or DisplayPort connectors in BTX-form-factor notebook/desktop PCs. It operates from a single +3.3V supply, supports >5Gbps data rates, delivers >12dB return loss at 2.5GHz, and integrates six bidirectional signal-pair switches in a 56-pin TQFN package.

For engineers reviewing the MAX4928BETN+T datasheet, MAX4928BETN+T pinout, MAX4928BETN+T application, or MAX4928BETN+T equivalent, key selection criteria include differential insertion loss at 5GHz, on-resistance matching across channels, latch-enabled state retention, and compatibility with PCIe Gen II and DisplayPort AC-coupled 8b/10b signaling.

Technical Context

The MAX4928BETN+T implements six independent bidirectional DPDT switch cells using CMOS architecture, each supporting differential signal routing between common terminals (IN_, X_, OUT_) and dual-destination terminals (D_/TX_, HPD_/RX1_, AUX_/RX0_). Its SEL input selects path direction while LE latches the configuration, enabling stable signal routing without continuous control signaling.

It is optimized for high-frequency integrity: differential -3dB bandwidth is 5GHz, insertion loss is -3.3dB at 5GHz, off-isolation reaches -22dB at 3GHz, and crosstalk remains below -23dB at 5GHz - all verified under 100Ω balanced termination per PCIe/DisplayPort channel requirements.

Key Specifications

Pinout & Package

MAX4928BETN+T is housed in a 5mm × 11mm, 56-pin TQFN-EP package with exposed paddle connected to GND for thermal and electrical stability. Pin assignments are industry-standard and optimized for high-speed layout: differential pairs are routed as adjacent pins with ground shielding, and VDD/GND pins are distributed to minimize supply noise.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed passive switch applications.

Compared with MAX4928AETN+, the MAX4928BETN+ provides identical high-speed switching performance but maps destination pins to prioritize BTX notebook layout conventions (e.g., HPD/RX routing on lower-numbered pins); versus TS3USB30E, it offers triple the channel count, DP/PCIe dual-mode support, and superior RF performance at the expense of larger footprint and higher pin count.

Availability

MAX4928BETN+T is available at Aetrix Electronics and suitable for PCIe graphics switching, DisplayPort multi-monitor routing, hot-plug detection systems, and multi-function port sharing requiring stable component supply and long-term lifecycle assurance.

Supply support for MAX4928BETN+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for computing, communications, and industrial applications.

The MAX4928 series belongs to Maxim's high-speed interface switch product line, engineered specifically for PCIe and DisplayPort signal routing in space-constrained, thermally demanding PC platforms where signal fidelity and layout efficiency are critical.

FAQ

What is the primary function of the MAX4928BETN+T in a PC platform?

The MAX4928BETN+T functions as a high-speed passive 6×DPDT analog switch that routes PCIe Gen I/II and DisplayPort differential signals between a graphics memory controller hub (GMCH) and either a PCIe connector or DisplayPort interface. It enables dynamic, low-latency switching without signal regeneration - preserving eye diagrams and timing margins essential for 5Gbps operation. The MAX4928BETN+T achieves this using CMOS switch cells with matched on-resistance and controlled impedance routing.

Does the MAX4928BETN+T support PCIe Gen III or higher data rates?

No, the MAX4928BETN+T is specified for PCIe Gen I and Gen II (up to 5Gbps), with differential -3dB bandwidth of 5GHz and insertion loss of −3.3dB at 5GHz. It does not meet the signal integrity requirements for PCIe Gen III (8Gbps) or Gen IV (16Gbps), which demand wider bandwidth (>8GHz) and lower loss (<−2dB at 4GHz). For Gen III+ applications, designers should evaluate newer-generation switches such as the MAX4929E or ADG1414-series alternatives.

How does the latch enable (LE) pin affect operation of the MAX4928BETN+T?

When LE is driven high, the MAX4928BETN+T holds its current switch configuration regardless of changes to the SEL input - effectively freezing the signal routing state. This prevents unintended switching during control signal transitions or noise events. When LE is low, SEL directly controls path selection in real time. The MAX4928BETN+T uses this feature to ensure glitch-free operation during system boot, hot-plug events, or firmware-controlled mode changes.

Can the MAX4928BETN+T be used for bidirectional signal routing in both PCIe and DisplayPort directions?

Yes, the MAX4928BETN+T is fully bidirectional: its IN_, X_, and OUT_ terminals can serve as inputs or outputs depending on system topology. For example, PCIe TX signals may originate from the GMCH and route to a connector (IN_ → TX_), or conversely, RX signals may enter via the connector and route to the GMCH (TX_ → IN_). This bidirectionality applies identically to DisplayPort D_, HPD_, AUX_, and RX_ paths - confirmed by the device's symmetric on-resistance and leakage specifications in both directions.

What is the recommended PCB layout practice for the MAX4928BETN+T to maintain signal integrity?

To preserve high-frequency performance, PCB layout for the MAX4928BETN+T must maintain controlled 100Ω differential impedance on all switched lanes, keep trace lengths short and matched within ±50µm, place 0.1µF ceramic bypass capacitors within 2mm of each VDD pin, connect the exposed paddle (EP) to a solid internal ground plane, and surround high-speed pins with ground guard traces. Avoid vias in differential paths, and ensure return paths are uninterrupted beneath signal layers - practices validated in Maxim's AN6317 layout guidelines for the MAX4928BETN+T.