Analog Devices Inc./Maxim Integrated MAX6714DUB+T
- Part No.:
- MAX6714DUB+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
MAX6714DUB+T.pdf
- Description:
- IC SUPERVISOR 4 CHANNEL 10UMAX
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
The MAX6714DUB+T from Maxim Integrated is a quad voltage monitor IC with integrated reset timing, designed for multivoltage system supervision. It monitors one fixed VCC supply (3.3V ±5%), three adjustable power-fail inputs (PFI1–PFI3) referenced to 0.62V, and delivers an active-low open-drain RESET output with 140ms minimum timeout - used in server power sequencing and telecom board-level supervision.
For engineers reviewing the MAX6714DUB+T datasheet, MAX6714DUB+T pinout, MAX6714DUB+T application, or MAX6714DUB+T equivalent, key selection criteria include its 3.3V VCC reset threshold, 0.62V internal reference for PFI inputs, 60µA typical supply current, 10-pin µMAX package, and guaranteed operation from –40°C to +85°C.
Technical Context
The MAX6714DUB+T implements a dedicated VCC monitoring path with internal undervoltage lockout and a fixed 3.3V ±5% reset threshold, plus three independent high-impedance PFI inputs each compared against a precision 0.62V bandgap reference. Its RESET output integrates a monolithic 140ms minimum timeout circuit triggered by either VCC dropout or manual reset assertion.
All outputs are active-low open-drain with 10µA internal pullup to VCC; the MR input features a 20kΩ internal pullup and supports TTL/CMOS logic levels. The device uses BiCMOS process technology and operates across 2.0V–5.5V supply range while maintaining ±2.0% threshold accuracy over temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Reset Threshold | 3.3V nominal with ±5% tolerance (2.85V to 3.00V trip range), enabling precise 3.3V rail supervision. |
| PFI Input Reference | 0.623V typical internal bandgap reference (±2.0% accuracy), supporting external resistor-divider–based monitoring down to 0.609V. |
| Reset Timeout Period | 140ms minimum (210ms typical), ensuring reliable microprocessor reset hold time without external RC components. |
| Supply Current | 60µA typical at 5V, enabling low-power system supervision in always-on embedded applications. |
| Operating Temperature | –40°C to +85°C extended range, qualified for industrial and telecom equipment deployment. |
| Package | 10-pin µMAX (3.0mm × 3.0mm × 0.8mm), surface-mount compatible with high-density PCB layouts. |
| Output Type | Active-low open-drain RESET and PFO outputs with 10µA internal pullup, allowing wire-ORing and flexible logic interfacing. |
Pinout & Package
Package: 10-pin µMAX (3.0mm × 3.0mm, 0.8mm height, exposed pad not electrically connected). Pin pitch: 0.5mm. RoHS-compliant lead-free packaging (+T suffix).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - PFI3 | Power-Fail Input 3 | High-impedance comparator input referenced to 0.62V; accepts external resistor-divider for adjustable voltage monitoring. |
| 2 - PFI2 | Power-Fail Input 2 | Identical function to PFI3; enables independent monitoring of two auxiliary rails (e.g., 1.2V, 1.8V, 2.5V). |
| 3 - PFI1 | Power-Fail Input 1 | Third adjustable monitor input; supports window detection or dual-rail fail-safe logic when combined with other PFI pins. |
| 4 - GND | Ground Reference | Analog/digital common return; requires low-impedance connection to system ground plane for noise immunity. |
| 5 - MR | Manual Reset Input | Active-low TTL/CMOS-compatible input with 20kΩ internal pullup; initiates RESET assertion on logic-low pulse ≥1µs. |
| 6 - RESET | Reset Output | Active-low open-drain output asserting for ≥140ms after VCC recovery or MR release; interfaces directly with µP reset pins. |
| 7 - PFO1 | Power-Fail Output 1 | Open-drain output asserting low when PFI1 falls below threshold; used for early warning or secondary reset generation. |
| 8 - PFO2 | Power-Fail Output 2 | Independent fail signal for second monitored rail; supports cascaded supervision or fault logging. |
| 9 - PFO3 | Power-Fail Output 3 | Third fail indicator; enables full tri-rail monitoring without external comparators or logic. |
| 10 - VCC | Supply Input | 2.0V–5.5V power input; powers internal circuitry and serves as reference for internal pullups and RESET timing. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 140ms reset timeout | Eliminates need for external RC timing network, reducing BOM count and layout area in space-constrained systems. |
| Three adjustable PFI inputs | Each references 0.62V internal bandgap, enabling accurate monitoring of any rail ≥0.62V via simple resistor dividers. |
| 0.3% threshold hysteresis | Built-in hysteresis prevents output oscillation during slow-moving or noisy supply transitions without external components. |
| 20kΩ internal MR pullup | Allows direct connection of momentary switch to GND without external biasing; simplifies manual reset implementation. |
| 10µA internal output pullups | Enables direct interface with 3.3V/5V logic families; external pullups to different voltages (≤5.5V) override internal sources safely. |
Applications
| Server Power Sequencing | Telecom Line Card Supervision |
|---|---|
Use Scenario: Monitoring 3.3V main rail and three auxiliary supplies (e.g., 1.2V core, 1.8V I/O, 2.5V analog) on a high-density server motherboard. IC Role / Device Role / Timing Role: MAX6714DUB+T acts as centralized power-good arbiter and reset generator, asserting RESET only after all four rails stabilize. Use Value: Ensures deterministic boot sequence and prevents processor corruption due to premature clock or data enablement. |
Use Scenario: Supervising multiple isolated DC/DC converters powering FPGA, PHY, and control logic on a carrier-grade line card. IC Role / Device Role / Timing Role: MAX6714DUB+T provides independent PFO signals per converter and a synchronized RESET for system-level fault containment. Use Value: Enables rapid identification of failed converter(s) and graceful shutdown before thermal or data integrity issues arise. |
| Industrial PLC Backplane | Network Switch ASIC Power Management |
Use Scenario: Validating 3.3V system rail and three field-side isolated supplies (24V→5V, 5V→3.3V, 3.3V→1.8V) in a programmable logic controller. IC Role / Device Role / Timing Role: MAX6714DUB+T serves as primary supervisor, using PFI inputs to detect upstream converter faults and trigger controlled I/O disable. Use Value: Prevents erroneous actuator commands during brownout conditions and meets SIL-2 functional safety requirements via deterministic reset behavior. |
Use Scenario: Managing power-up sequencing and runtime monitoring of multi-rail ASIC supply domains (core, I/O, PLL, memory) in a 10G Ethernet switch. IC Role / Device Role / Timing Role: MAX6714DUB+T generates RESET for the ASIC and feeds PFO outputs to FPGA-based health monitor for real-time rail diagnostics. Use Value: Reduces firmware complexity by offloading critical timing and threshold validation to hardware, improving system MTBF. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad voltage monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6714CUB+T | VCC threshold set to 3.3V ±10% (2.85V–3.00V vs. 2.93V–3.00V), higher trip hysteresis margin. | Suitable where looser 3.3V tolerance is acceptable (e.g., non-critical auxiliary rails), offering greater noise immunity. | Select MAX6714CUB+T if system design allows wider VCC trip window and prioritizes robustness over tight reset timing. |
| TPS3808G33DBVR | Single-supply monitor (3.3V only), no PFI inputs, 200ms fixed timeout, 1.6µA quiescent current. | Limited to basic VCC supervision; lacks multi-rail monitoring capability and manual reset input. | Choose TPS3808G33DBVR only for cost-sensitive single-rail applications where PFI functionality is unnecessary. |
Compared with MAX6714CUB+T and TPS3808G33DBVR, the MAX6714DUB+T uniquely combines tight 3.3V ±5% reset accuracy, three configurable PFI inputs, and integrated 140ms timeout - making it optimal for multirail systems requiring both precision and flexibility.
Availability
MAX6714DUB+T is available at Aetrix Electronics and suitable for server power sequencing, telecom line card supervision, and industrial PLC backplane applications requiring stable component supply, long-term lifecycle support, and guaranteed performance across –40°C to +85°C.
Supply support for MAX6714DUB+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for power management, sensing, and interface applications, with emphasis on high-reliability industrial and communications systems.
The MAX6714DUB+T belongs to Maxim's voltage supervisor product line, engineered specifically for multivoltage system monitoring where simultaneous rail validation, deterministic reset timing, and minimal external components are required.
FAQ
What is the exact VCC reset threshold voltage for MAX6714DUB+T?
The MAX6714DUB+T has a factory-trimmed VCC reset threshold of 3.3V nominal with ±5% tolerance, resulting in a guaranteed trip range of 2.93V to 3.00V (min to max) when VCC falls. This value is specified in the Electrical Characteristics table for MAX6714 under "VCC Reset Threshold" and applies exclusively to the D-suffix variant.
Can MAX6714DUB+T monitor a 1.2V supply, and how is it configured?
Yes, the MAX6714DUB+T can monitor a 1.2V supply using any of its three PFI inputs (PFI1–PFI3). Since each PFI input compares against a 0.623V internal reference, a resistor divider (e.g., R1 = 93kΩ, R2 = 100kΩ) scales 1.2V down to ~0.62V at the PFI pin. The MAX6714DUB+T datasheet Figure 7 provides the exact calculation: R1 = R2 × (VINTH/0.62V − 1).
Does MAX6714DUB+T require external components for basic reset functionality?
No, the MAX6714DUB+T requires no external components for core reset operation: its 140ms timeout, 3.3V VCC threshold, and 0.62V PFI reference are fully internal. Only optional features - such as manual reset (MR switch), external pullups for level-shifting, or resistor dividers for PFI inputs - demand external parts. The base RESET assertion on VCC dropout is self-contained.
What is the maximum sink current supported by the RESET output of MAX6714DUB+T?
The RESET output of MAX6714DUB+T is an open-drain structure rated for 2mA sink current at VCC = 5V (VOL ≤ 0.3V), per the Electrical Characteristics table. At lower VCC (e.g., 2.5V), it supports 1.2mA. This allows direct interfacing with most µP reset inputs without external drivers, provided the load does not exceed these limits.
How does the MR input behave when left unconnected on MAX6714DUB+T?
When left unconnected, the MR input of MAX6714DUB+T remains pulled high internally by a 20kΩ resistor to VCC, keeping RESET deasserted under normal operation. No external pullup is needed. However, in noisy environments or with long PCB traces, adding a 0.1µF capacitor from MR to GND is recommended to suppress false resets caused by EMI or transients.
MAX6714DUB+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 4
- Voltage - Threshold:
- 3.08V, Adj, Adj, Adj
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-uMAX/uSOP
MAX6714DUB+T FAQ
1.How can I place an order for MAX6714DUB+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX6714DUB+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX6714DUB+T reliable?
The price and inventory of MAX6714DUB+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6714DUB+T is usually 5 days.
3.What payment methods are accepted for MAX6714DUB+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6714DUB+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX6714DUB+T?
MAX6714DUB+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX6714DUB+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX6714DUB+T?
For technical support, including MAX6714DUB+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6714DUB+T requirements.
6.How does Aetrix verify that MAX6714DUB+T is sourced from the original manufacturer or authorized distributors?
All MAX6714DUB+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6714DUB+T meets industry standards.
7.What is the process for return or replacement of MAX6714DUB+T?
All MAX6714DUB+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX6714DUB+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX6714DUB+T part is unused and in its original packaging.
Return procedure for MAX6714DUB+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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