Analog Devices Inc./Maxim Integrated MAX6728KAWGD3+
- Part No.:
- MAX6728KAWGD3+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- -
- Datasheet:
-
MAX6728KAWGD3+.pdf
- Description:
- IC SUPERVISOR
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Product details
Overview
MAX6728KAWGD3+ from Maxim Integrated is a triple-voltage microprocessor supervisory circuit in an 8-pin SOT23 package, monitoring VCC1 (primary), VCC2 (secondary), and PFI (power-fail input) with factory-trimmed thresholds of 4.625V (VTH1), 3.075V (VTH2), and 626.5mV (VPFI). It provides open-drain active-low RST and PFO outputs, manual reset input (MR), and a 280ms minimum reset timeout period. It ensures reliable system reset in multivoltage embedded power management applications.
For engineers reviewing the MAX6728KAWGD3+ datasheet, MAX6728KAWGD3+ pinout, MAX6728KAWGD3+ application, or MAX6728KAWGD3+ equivalent, key selection criteria include its triple-supply monitoring capability, guaranteed reset validity down to VCC1/VCC2 = 0.8V, low 14µA typical supply current at 3.6V, immunity to short VCC transients, and support for power-fail warning with 2µs PFI-to-PFO delay.
Technical Context
The MAX6728KAWGD3+ integrates three independent voltage comparators: one for VCC1 (4.625V threshold), one for VCC2 (3.075V threshold), and one for PFI (626.5mV reference), all with 20ppm/°C tempco and 0.5% hysteresis. Its reset logic asserts RST when any monitored voltage falls below its threshold and holds it for 280ms after recovery.
It features an open-drain PFO output that deasserts immediately upon PFI recovery-without timeout-enabling fast power-fail interrupt signaling. The MR input includes a 50kΩ internal pullup to VCC1 and supports 1µs minimum pulse width with 100ns glitch rejection, ensuring robust manual reset initiation in noisy environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC1 Threshold | 4.625V (factory-trimmed, ±125mV tolerance); ensures precise brownout detection on primary 5V or 4.8V rails |
| VCC2 Threshold | 3.075V (factory-trimmed, ±75mV tolerance); monitors secondary 3.3V supplies with tight margin |
| PFI Threshold | 626.5mV (internal reference); enables accurate external resistor-divider-based monitoring of auxiliary supplies down to 0.62V |
| Reset Timeout | 280ms (minimum); guarantees sufficient hold time for full processor initialization and memory stabilization |
| Supply Current | 14µA (typical at 3.6V); minimizes quiescent power draw in battery-operated or always-on systems |
| Operating Temp | -40°C to +85°C; qualified for industrial and telecom equipment deployment without derating |
| VCC Validity | Reset output guaranteed valid down to VCC1 or VCC2 = 0.8V; supports ultra-low-voltage brownout detection during deep power-down |
Pinout & Package
MAX6728KAWGD3+ uses an 8-pin SOT23-8 package with exposed pad (thermal enhancement), footprint-compatible with industry-standard 8-pin SOT23 layouts and reflow-solderable per JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | RST | Active-low open-drain reset output; requires external pullup; asserts when VCC1, VCC2, or PFI drops below threshold |
| 2 | GND | Ground reference for all internal comparators and logic; must be low-impedance connection to system ground plane |
| 3 | MR | Active-low manual reset input; internally pulled up to VCC1 (50kΩ); initiates reset on falling edge ≥1µs wide |
| 4 | PFO | Active-low open-drain power-fail output; asserts when PFI < 626.5mV; deasserts immediately on recovery (no timeout) |
| 5 | VCC2 | Secondary supply input (0.9V–3.3V range); powers internal VCC2 comparator and sets RST2 reference if used |
| 6 | VCC1 | Primary supply input (1.8V–5.0V range); powers core logic, sets RST reference, and sources MR pullup |
| 7 | PFI | Power-fail monitor input; high-impedance (±25nA); connects to resistor divider for custom trip point; referenced to 626.5mV internal VREF |
| 8 | NC | No connect; internally unconnected; must remain floating or tied to GND per layout best practice |
Key Features
| Feature | Design Value |
|---|---|
| Triple-voltage supervision | Simultaneous monitoring of VCC1, VCC2, and PFI enables single-chip protection for complex multirail systems (e.g., CPU + I/O + backup rail) |
| Open-drain PFO with zero-delay deassertion | Allows immediate µP interrupt generation on power-up without waiting for reset timeout, enabling faster firmware response to power-good events |
| Guaranteed reset validity to 0.8V | Ensures deterministic reset behavior during deep brownout conditions where other supervisors may fail or oscillate |
| 20ppm/°C threshold tempco | Maintains voltage threshold accuracy across industrial temperature range, reducing need for system-level calibration |
| 14µA typical ICC at 3.6V | Extends battery life in portable equipment and reduces self-heating in thermally constrained enclosures |
Applications
| Server Power Sequencing | Industrial PLC Controller |
|---|---|
Use Scenario: Monitoring 5V primary, 3.3V I/O, and 12V auxiliary rails during cold start and hot-swap events in 1U rack servers. IC Role / Device Role / Timing Role: Triple-supply supervisor asserting coordinated RST and PFO signals to ensure proper boot order and early power-fail warning before main CPU initialization. Use Value: Prevents corrupted firmware execution by holding reset until all rails stabilize above 4.625V, 3.075V, and derived PFI threshold-verified across -40°C to +85°C. | Use Scenario: Supervising 24V DC input, 5V logic, and 3.3V FPGA core in programmable logic controller backplanes exposed to EMI-rich factory floors. IC Role / Device Role / Timing Role: Fault-detection hub providing MR-initiated safe shutdown, PFI-triggered watchdog disable, and noise-immune reset assertion via 100ns glitch rejection. Use Value: Eliminates need for discrete RC timers and comparator networks, reducing BOM count by 4 components while improving timing repeatability to ±0.5%. |
| Medical Imaging Module | 5G Small Cell Radio |
Use Scenario: Ensuring clean startup of X-ray detector ASICs powered by isolated 3.3V, 1.8V, and analog 5V supplies in portable ultrasound units. IC Role / Device Role / Timing Role: Precision voltage guardian validating all three rails prior to enabling high-speed ADC clocks and sensor biasing circuits. Use Value: Achieves <100ppm false-reset rate over lifetime due to 0.5% hysteresis and 20ppm/°C tempco-critical for FDA-compliant diagnostic accuracy. | Use Scenario: Managing power integrity for RF transceiver SoCs requiring strict sequencing between 48V PoE-derived 12V, 5V LDO, and 1.0V core rails in outdoor base stations. IC Role / Device Role / Timing Role: Dual-role supervisor: RST enforces boot sequence compliance; PFO feeds FPGA interrupt to initiate graceful RF power ramp-down on AC line sag. Use Value: Enables sub-2ms power-fail response (2µs PFI→PFO delay + FPGA ISR latency), preventing packet loss during grid fluctuations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-voltage supervisory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6729KA+T | Push-pull PFO output instead of open-drain; identical VTH1/VTH2/PFI thresholds and 280ms timeout | Requires no external pullup on PFO; better suited for driving CMOS inputs directly but lacks flexibility for wired-OR interrupt buses | Select MAX6729KA+T when PFO must drive a CMOS gate without external components; otherwise MAX6728KAWGD3+ offers greater interface versatility |
| TPS3808G33DBVR | Dual-supply monitor only (VDD1/VDD2); no PFI input; fixed 3.3V/3.075V thresholds; 200ms timeout; SOT23-6 package | Lacks third-supply monitoring and power-fail interrupt capability; smaller footprint but requires external circuitry for auxiliary rail supervision | Choose TPS3808G33DBVR only if system has exactly two critical rails and space constraints prohibit 8-pin SOT23; MAX6728KAWGD3+ is required for true triple-rail coverage |
Compared with MAX6729KA+T, MAX6728KAWGD3+ provides open-drain PFO for shared interrupt lines, while versus TPS3808G33DBVR it delivers essential third-rail supervision and PFI functionality-making it the only drop-in solution for designs requiring simultaneous VCC1/VCC2/PFI monitoring in a single IC.
Availability
MAX6728KAWGD3+ is available at Aetrix Electronics and suitable for server power sequencing, industrial PLC controllers, medical imaging modules, and 5G small cell radios requiring stable component supply with full traceability and long-term lifecycle support.
Supply support for MAX6728KAWGD3+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for power management, sensing, and connectivity in demanding industrial, automotive, and communications systems.
The MAX6715–MAX6729 family was engineered specifically for multivoltage microprocessor systems needing compact, low-power, triple-rail supervision with guaranteed operation down to 0.8V supply-targeting telecom infrastructure, embedded computing, and portable medical devices.
FAQ
What is the exact reset threshold voltage for VCC1 on the MAX6728KAWGD3+?
The MAX6728KAWGD3+ has a factory-trimmed VCC1 reset threshold of 4.625V (minimum 4.500V, maximum 4.750V) with 0.5% hysteresis and 20ppm/°C temperature coefficient. This value is encoded in the "K" suffix per Maxim's Reset Voltage Threshold Suffix Guide and is verified across the full -40°C to +85°C operating range. The MAX6728KAWGD3+ uses this precise threshold to detect brownout on 5V or 4.8V primary rails before system instability occurs.
Does the MAX6728KAWGD3+ support monitoring a negative supply voltage?
Yes, the MAX6728KAWGD3+ can monitor negative supplies using the PFI input with an appropriate resistor-divider network as shown in Figure 3b of the datasheet. When a negative rail drops, PFI falls below 626.5mV and PFO asserts low. Accuracy depends on PFI input tolerance (±25nA), resistor matching, and VCC stability. The MAX6728KAWGD3+ does not require level-shifting circuitry-its PFI comparator operates referenced to GND, enabling direct negative-rail monitoring with proper external biasing.
What is the function of Pin 8 (NC) on the MAX6728KAWGD3+?
Pin 8 on the MAX6728KAWGD3+ is a no-connect (NC) terminal-internally unconnected and electrically isolated from all circuitry. It must remain floating in the PCB layout; tying it to GND is permissible per Maxim's layout recommendations to improve thermal dissipation and mechanical stability, but connecting it to any active net will cause undefined behavior. This NC pin is part of the 8-pin SOT23-8 package standard and does not affect MAX6728KAWGD3+ functionality whether left open or grounded.
How does the manual reset (MR) input behave during power-up of the MAX6728KAWGD3+?
During power-up, the MR input of the MAX6728KAWGD3+ is internally pulled up to VCC1 via a 50kΩ resistor, holding it high and preventing spurious reset assertion. Once VCC1 reaches 0.8V, the internal logic becomes active and MR is fully functional. A low pulse ≥1µs on MR forces RST assertion for the full 280ms timeout period, even if VCC1/VCC2/PFI remain valid. The MAX6728KAWGD3+ also rejects glitches <100ns, ensuring noise immunity during system startup transients.
Can the MAX6728KAWGD3+ be used without connecting the PFI pin?
Yes, the PFI pin on the MAX6728KAWGD3+ may be left unconnected, tied to GND, or connected to VCC1/VCC2 if unused-per Maxim's recommendation in the Pin Description table. Leaving PFI unconnected disables the power-fail monitoring function but does not affect VCC1/VCC2 supervision or MR operation. The MAX6728KAWGD3+ continues full dual-supply monitoring with RST assertion based solely on VCC1 and VCC2 thresholds, maintaining all specified timing and electrical performance.
MAX6728KAWGD3+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- -
- Number of Voltages Monitored:
- -
- Voltage - Threshold:
- -
- Output:
- -
- Reset:
- -
- Reset Timeout:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
MAX6728KAWGD3+ FAQ
1.How can I place an order for MAX6728KAWGD3+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX6728KAWGD3+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX6728KAWGD3+ reliable?
The price and inventory of MAX6728KAWGD3+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6728KAWGD3+ is usually 5 days.
3.What payment methods are accepted for MAX6728KAWGD3+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6728KAWGD3+ transactions.
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4.How is shipping managed for MAX6728KAWGD3+?
MAX6728KAWGD3+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX6728KAWGD3+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX6728KAWGD3+?
For technical support, including MAX6728KAWGD3+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6728KAWGD3+ requirements.
6.How does Aetrix verify that MAX6728KAWGD3+ is sourced from the original manufacturer or authorized distributors?
All MAX6728KAWGD3+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6728KAWGD3+ meets industry standards.
7.What is the process for return or replacement of MAX6728KAWGD3+?
All MAX6728KAWGD3+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX6728KAWGD3+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX6728KAWGD3+ part is unused and in its original packaging.
Return procedure for MAX6728KAWGD3+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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