Analog Devices Inc./Maxim Integrated MAX685ETG+

Overview

MAX685ETG+ from Maxim Integrated is a dual-output, positive-and-negative DC-DC converter IC designed for powering CCD imaging devices and LCD bias rails. It delivers up to +24V/10mA and −9V/10mA from a +2.7V to +5.5V input using a single inductor, features 30mV_p-p output ripple, fixed-frequency PWM operation at 220kHz or 400kHz, and integrated power switches in a 24-pin 4mm × 4mm Thin QFN package.

For engineers reviewing the MAX685ETG+ datasheet, MAX685ETG+ pinout, MAX685ETG+ application, or MAX685ETG+ equivalent, key selection considerations include independent positive/negative output regulation, selectable power-on sequencing (SEQ), power-OK indicator (POK), logic-controlled shutdown (0.1µA), and external clock synchronization capability (200–480kHz).

Technical Context

The MAX685ETG+ employs current-mode PWM control with alternating step-up and inverting cycles per oscillator period-each output regulator operates at half the oscillator frequency (e.g., 110kHz or 200kHz). Regulation is achieved via separate feedback paths: FBP senses the positive output against a 1.25V internal reference, while FBN senses the negative output referenced to REF.

It integrates P-channel and N-channel MOSFETs on LXP and LXN, supports programmable startup order via SEQ, and uses an open-drain POK output that asserts low when either output falls below 90% of regulation. The device includes undervoltage lockout (UVLO: 2.5V typ) and internal 1.25V reference with ±0.5% accuracy over temperature.

Key Specifications

Pinout & Package

MAX685ETG+ is housed in a 24-pin, 4mm × 4mm × 0.8mm Thin QFN package with exposed thermal pad (PGND-connected). Pin 1 marked by dot; pins 13–14 and 15–17 are PGND; pins 19 and 24 are N.C.; pin 11 is REF; pins 12 and 10 are FBP and FBN respectively.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output DC-DC converter applications.

Compared with MAX686ETG+, MAX685ETG+ trades −12V capability for tighter −9V spec and lower cost; versus TPS65131RGTR, it provides full output adjustability, SEQ control, and lower-frequency operation for improved filter design and noise margin.

Availability

MAX685ETG+ is available at Aetrix Electronics and suitable for CCD imaging systems, LCD bias generation, and portable digital camera modules requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for MAX685ETG+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, medical, communications, and consumer applications.

The MAX685ETG+ belongs to Maxim's high-efficiency, low-noise DC-DC converter product line, engineered specifically for imaging and display subsystems requiring tightly regulated dual-rail bias with minimal board area and EMI impact.

FAQ

What is the maximum achievable output voltage range for MAX685ETG+?

The MAX685ETG+ delivers +24V and −9V with internal feedback; with external charge-pump components (as shown in Figure 4 of the datasheet), it supports up to +45V and −16V. However, the absolute voltage between VDD and VOUT− must not exceed 14.5V. The MAX685ETG+ achieves this using its dual-switch architecture and dedicated FBP/FBN feedback paths, enabling independent rail optimization without compromising regulation accuracy.

How does the SEQ pin affect power-up behavior in MAX685ETG+?

The SEQ pin determines startup order: when SEQ = GND, the negative output powers first and stabilizes before enabling the positive output; when SEQ = VDD, the positive output powers first. This prevents reverse-bias conditions in CCD arrays or LCD driver ICs. The MAX685ETG+ monitors each output against 90% of its target voltage before proceeding-ensuring safe, controlled sequencing without external controllers.

Can MAX685ETG+ be synchronized to an external clock, and what is the valid frequency range?

Yes, the MAX685ETG+ SYNC pin accepts an external clock from 200kHz to 480kHz. Internally, it runs at 220kHz (SYNC = GND) or 400kHz (SYNC = VDD). When synchronized, each output switches at half the applied clock frequency-so a 400kHz sync signal yields 200kHz per rail. This capability allows EMI reduction and timing alignment in systems with master clocks, a key advantage of the MAX685ETG+ over fixed-frequency-only alternatives.

What is the role of the POK output in MAX685ETG+, and how should it be interfaced?

The POK (Power-OK) output is an open-drain signal that goes high-impedance when both outputs are within 90% of regulation, and pulls low otherwise. It requires a 100kΩ pull-up to VDD and can sink up to 2mA. During shutdown, POK remains high-impedance. This feature enables system-level power validation-microcontrollers can monitor POK to confirm rail readiness before initiating CCD readout or LCD initialization sequences in the MAX685ETG+ design.

Does MAX685ETG+ integrate power switches, and what are their on-resistance values?

Yes, the MAX685ETG+ integrates both P-channel (LXP) and N-channel (LXN) MOSFETs. Typical on-resistance is 0.6Ω for LXP and 2Ω for LXN (at VDD = 5V), enabling efficient operation at 10mA loads without external switches. These integrated switches eliminate external transistor count and gate-drive complexity-critical for minimizing solution size in compact imaging modules using the MAX685ETG+.