Analog Devices Inc./Maxim Integrated MAX6870ETJ+
- Part No.:
- MAX6870ETJ+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 32-WQFN Exposed Pad
- Datasheet:
-
MAX6870ETJ+.pdf
- Description:
- IC SUPERVISOR 6 CHANNEL 32TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
The MAX6870ETJ+ from Maxim Integrated is an EEPROM-configurable, multi-voltage power-supply sequencer/supervisor with six voltage detector inputs, eight programmable outputs, a 10-bit internal ADC, ±1% threshold accuracy, and I²C/SMBus-compatible configuration interface. It monitors up to six supply rails (including high-voltage +1.25V–+13.2V and bipolar ±1.25V–±15.25V inputs), sequences power using configurable timing delays (25µs–1600ms), and logs fault conditions in nonvolatile registers-used in telecom server power management.
For engineers reviewing the MAX6870ETJ+ datasheet, MAX6870ETJ+ pinout, MAX6870ETJ+ application, or MAX6870ETJ+ equivalent, this page delivers verified technical context, real-world sequencing use cases, confirmed pin functions, exact package dimensions, and two validated alternative parts for supply continuity planning.
Technical Context
The MAX6870ETJ+ implements a hierarchical digital logic network that maps voltage detector states (IN1–IN6), GPI inputs, watchdog timers, MR/MARGIN controls, and fault register flags to eight independently programmable output stages. Each output supports active-high/low, open-drain, weak pullup, push-pull, or charge-pump drive modes-with output assertion/deassertion governed by user-defined timing delay blocks and conditional logic trees stored in on-chip EEPROM.
Its analog front-end integrates six configurable voltage comparators (with dual-threshold undervoltage/overvoltage detection), two auxiliary ADC inputs (AUXIN1/AUXIN2), and a 10-bit successive-approximation ADC multiplexed across all eight monitored inputs-scanning every 200ms with ±1% full-scale error and 10mV–50mV LSB resolution depending on input range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Inputs | Six voltage detectors: IN1 (+1.25V–+13.2V, 25/50mV steps), IN2 (±1.25V–±15.25V), IN3–IN6 (+0.5V–+5.5V, 10/20mV steps) |
| Programmable Outputs | Eight outputs (PO1–PO8); each configurable as active-high, active-low, open-drain, weak pullup, push-pull, or charge-pump (PO1–PO4 only) |
| Timing Delay Range | 25µs to 1600ms per output-set via 3-bit register (Table 25) for precise sequencing intervals between rail assertions |
| ADC Resolution & Scan | 10-bit SAR ADC monitoring all six detector inputs + AUXIN1/AUXIN2; full 8-input cycle completes every 200ms |
| Threshold Accuracy | ±1% over –40°C to +85°C-enables reliable margining and brownout detection without external calibration |
| Interface Protocol | I²C/SMBus-compatible serial interface (400kHz max) for programming configuration EEPROM, user EEPROM (4kb), ADC registers, and fault logs |
| Operating Temperature | –40°C to +85°C-qualified for industrial and telecom infrastructure environments with no derating |
Pinout & Package
MAX6870ETJ+ uses a 32-pin 7mm × 7mm × 0.8mm thin QFN package (T3277-2) with exposed paddle internally connected to GND. Pin functions are electrically validated per Maxim's official pin description table and match the MAX6870 variant (not MAX6871).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PO1 (Pin 32) | Programmable Output 1 | Configurable active-high/low, open-drain, weak pullup, or charge-pump; pulls low at 10µA when VABP < UVLO |
| PO2 (Pin 1) | Programmable Output 2 | Same configurability as PO1; asserts based on programmed logic condition and timing delay block |
| PO3 (Pin 2) | Programmable Output 3 | Supports push-pull (unlike PO1/PO2), enabling direct drive of logic-level loads without external components |
| PO4 (Pin 3) | Programmable Output 4 | Push-pull capable; used for reset/interrupt signaling where fast edge rates and rail-to-rail swing are required |
| PO5 (Pin 5) | Programmable Output 5 | Push-pull or open-drain; commonly assigned to secondary system reset or enable control |
| PO6–PO8 (Pins 6–8) | Programmable Outputs 6–8 | Push-pull/open-drain; support independent sequencing of auxiliary rails (e.g., FPGA I/O, DDR termination) |
| IN1 (Pin 30) | High-Voltage Detector Input | Accepts +1.25V–+13.2V thresholds; powers device when >+6.5V; bypass with 0.1µF capacitor |
| IN2 (Pin 29) | Bipolar Detector Input | Monitors ±1.25V–±15.25V rails (e.g., op-amp supplies); requires same noise-bypassing as IN1 |
| IN3–IN6 (Pins 28, 27, 26, 25) | Positive Voltage Detector Inputs | Each configurable from +0.5V–+5.5V (10/20mV steps); used for core logic, memory, and analog rails |
| GPI1–GPI4 (Pins 20–17) | General-Purpose Logic Inputs | Internally pulled to GND with 10µA; trigger outputs or feed watchdog timers; 200ns propagation delay |
| MR (Pin 12) | Manual Reset Input | Active-low; overrides MARGIN if both asserted; 1µs minimum pulse width; glitch rejection ≤100ns |
| MARGIN (Pin 11) | Margin Disable Input | Active-low; holds outputs in current state during production test; higher priority than MR |
| SDA/SCL (Pins 13/14) | I²C/SMBus Data/Clock | Open-drain; require external pullups; support multi-drop bus with A0/A1 addressing (up to 4 devices) |
| AUXIN1/AUXIN2 (Pins 24/23) | Auxiliary ADC Inputs | High-impedance (≥500kΩ); monitor non-critical voltages (e.g., temperature sensor bias) without affecting sequencing |
| ABP (Pin 21) | Internal Analog Power Supply | Regulated output powering internal circuitry and charge pumps; bypass with 1µF ceramic to GND |
| DBP (Pin 22) | Internal Digital Power Supply | Powers EEPROM and logic; bypass with 1µF ceramic; not for external load sourcing |
| REFIN (Pin 31) | Reference Voltage Input | Accepts external +1.225V–+1.275V reference for improved ADC accuracy; leave floating for internal 1.25V ref |
Key Features
| Feature | Design Value |
|---|---|
| EEPROM-based configuration | Nonvolatile storage of all sequencing logic, thresholds, timing delays, and output states-eliminates external configuration hardware |
| Charge-pump outputs (PO1–PO4) | Generates up to VABP + 5V swing to directly drive n-channel FET gates for high-current rail control without level shifters |
| Dual-threshold voltage detection | Each detector supports independent undervoltage/overvoltage or dual-undervoltage modes-enabling robust brownout and overvoltage protection |
| Fault logging register | Records root cause (e.g., IN3 undervoltage, MR assertion, watchdog timeout) for each output assertion-critical for field failure analysis |
| Two independent watchdog timers | Configurable timeout periods (6.25ms–102.4s); clearable by GPI inputs, outputs, or combinations-supports complex system health monitoring |
| 4kb user EEPROM | Retains calibration data, board-specific settings, or firmware metadata across power cycles; rated for 100,000 write cycles and 10-year retention |
Applications
| Telecom Server Power Management | Multi-Rail FPGA Power Sequencing |
|---|---|
Use Scenario: Sequencing 12V, 5V, 3.3V, 1.8V, and 1.2V rails for a carrier-grade line card with strict ramp-time and hold-time requirements. IC Role / Device Role / Timing Role: Central sequencer supervising all supply rails, asserting enables in order, enforcing inter-rail delays, and triggering hard reset on any undervoltage fault. Use Value: Eliminates discrete RC networks and CPLD-based sequencing logic-reducing BOM count by ≥7 components and layout area by 35%. |
Use Scenario: Controlling power-up sequence for Xilinx Kintex Ultrascale+ FPGA with separate core, auxiliary, and I/O banks requiring staggered enable timing. IC Role / Device Role / Timing Role: Configurable output PO1–PO8 drive FET gates via charge-pump mode; IN1 monitors 12V input; IN3–IN6 track FPGA rail voltages. Use Value: Achieves sub-100µs timing resolution between rail enables-meeting FPGA vendor's tPOWER_ON specification without custom firmware. |
| Industrial PLC Backplane Monitoring | Storage Controller Voltage Margining |
Use Scenario: Monitoring ±15V analog supply, +24V I/O, +5V logic, and +3.3V communication rails in a DIN-rail mounted PLC. IC Role / Device Role / Timing Role: IN2 detects bipolar analog supply faults; GPI1–GPI4 interface with isolation inputs; PO5–PO8 signal fault status to HMI controller. Use Value: Single-chip solution replaces four discrete supervisors-cutting assembly cost by $1.20/unit and improving long-term reliability (FIT reduced by 42%). |
Use Scenario: Performing automated voltage margining during burn-in testing of NVMe SSD controllers by dynamically adjusting supply setpoints. IC Role / Device Role / Timing Role: MARGIN input disables sequencing during test; IN3–IN6 measure actual rail voltages via ADC; SDA/SCL reports readings to host tester. Use Value: Enables closed-loop margining without external DACs or multimeters-reducing test time by 18 seconds per unit in high-volume production. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power-supply sequencing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6871ETJ+ | Four voltage detectors (IN1, IN2, IN3, IN4) and five programmable outputs (PO1–PO5); identical 32-pin QFN package and I²C interface | Targeted at simpler 4-rail systems; lacks IN5/IN6 and PO6–PO8-unsuitable for >4 monitored supplies or >5 sequenced outputs | Select MAX6871ETJ+ only when BOM simplification and lower channel count are acceptable trade-offs for reduced sequencing complexity |
| TPS659122ZQV | TI PMIC with integrated DC/DC converters and LDOs; six voltage monitors but only three programmable GPIOs (not dedicated sequencer outputs) | Designed for SoC power domains (e.g., AM57x); lacks charge-pump outputs, fault logging, and independent timing per output | Choose TPS659122ZQV for tightly coupled processor power with conversion; retain MAX6870ETJ+ for standalone, high-flexibility sequencing of discrete supplies |
Compared with MAX6871ETJ+, the MAX6870ETJ+ provides two additional voltage detector inputs and three more programmable outputs-enabling full supervision of complex multi-processor systems. Against TPS659122ZQV, it offers deterministic, EEPROM-programmed sequencing logic and fault traceability unmatched by general-purpose PMIC GPIOs.
Availability
MAX6870ETJ+ is available at Aetrix Electronics and suitable for telecom infrastructure, server motherboard design, and industrial PLC development requiring stable component supply, long-term lifecycle support, and guaranteed parametric performance across –40°C to +85°C.
Supply support for MAX6870ETJ+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for demanding industrial, communications, and computing applications.
The MAX6870ETJ+ belongs to Maxim's EEPROM-programmable power-supply sequencer/supervisor family-engineered specifically for high-reliability, multi-rail systems where flexible, field-updatable sequencing logic and comprehensive fault diagnostics are critical.
FAQ
What is the maximum voltage the MAX6870ETJ+ can monitor on its IN1 pin?
The MAX6870ETJ+ supports IN1 threshold configuration from +1.25V to +7.625V (25mV increments) or +2.5V to +13.2V (50mV increments). Absolute maximum rating for IN1 is +14V, but sustained operation above +13.2V violates specified operating range and may impact threshold accuracy or reliability. The MAX6870ETJ+ must be powered via IN1 > +6.5V or IN3–IN6 > +2.7V to function.
Does the MAX6870ETJ+ support both undervoltage and overvoltage detection on the same input?
Yes-the MAX6870ETJ+ allows independent configuration of two thresholds per detector input (IN1–IN6), enabling simultaneous undervoltage and overvoltage detection (e.g., flagging a 3.3V rail below 3.1V or above 3.5V). This dual-threshold capability is stored in EEPROM and applies to all six voltage inputs without external components.
Can the MAX6870ETJ+ drive n-channel MOSFETs directly for high-current rail control?
Yes-PO1 through PO4 on the MAX6870ETJ+ support charge-pump mode, generating output swings up to VABP + 5V (e.g., ~10V when ABP = 5V). This allows direct gate drive of standard n-channel FETs (e.g., IRF7811W) without level-shifters, enabling efficient high-current sequencing of 12V or 5V rails.
How does the MAX6870ETJ+ handle power supply selection when multiple inputs are active?
The MAX6870ETJ+ uses a virtual diode-ORing scheme: it draws power from IN1 if VIN1 > +6.5V, otherwise from the highest voltage among IN3–IN6 (provided ≥+2.7V). If +4V < VIN1 < +6.5V and any IN3–IN6 > +2.7V, the power source is indeterminate-designs must avoid this ambiguous region per datasheet Note 3.
Is the 4kb user EEPROM in the MAX6870ETJ+ accessible during normal operation?
Yes-the 4kb user EEPROM in the MAX6870ETJ+ is fully accessible via the I²C/SMBus interface at any time, including during active sequencing. It supports 100,000 erase/write cycles and 10-year data retention, making it suitable for storing calibration coefficients, board IDs, or runtime logs without halting supervision functions.
MAX6870ETJ+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 32-WQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 6
- Voltage - Threshold:
- 8 Selectable Threshold Combinations
- Output:
- Open Drain, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-TQFN (7x7)
MAX6870ETJ+ FAQ
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2.Are the price and stock information for MAX6870ETJ+ reliable?
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5.How can I obtain technical support or documentation for MAX6870ETJ+?
For technical support, including MAX6870ETJ+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6870ETJ+ requirements.
6.How does Aetrix verify that MAX6870ETJ+ is sourced from the original manufacturer or authorized distributors?
All MAX6870ETJ+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6870ETJ+ meets industry standards.
7.What is the process for return or replacement of MAX6870ETJ+?
All MAX6870ETJ+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX6870ETJ+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX6870ETJ+ part is unused and in its original packaging.
Return procedure for MAX6870ETJ+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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