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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Analog Devices Inc./Maxim Integrated MAX6871ETJ+

Name: MAX6871ETJ+
Brand: Analog Devices Inc./Maxim Integrated
SKU: MAX6871ETJ+
Price: 2.40 USD
Availability: InStock
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Part No.:: MAX6871ETJ+

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Supervisors

Package:: 32-WFQFN Exposed Pad

Datasheet:: MAX6871ETJ+.pdf

Description:: IC SEQUENCE/SUPERVISOR 32TQFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

The MAX6871ETJ+ from Maxim Integrated is a 4-input, 5-output EEPROM-programmable power-supply sequencer/supervisor with integrated 10-bit ADC, ±1% threshold accuracy, and I²C/SMBus interface. It monitors four positive voltage inputs (IN3–IN4), one high-voltage input (IN1), one bipolar input (IN2), two auxiliary analog inputs (AUXIN1/AUXIN2), and four logic inputs (GPI1–GPI4) to control sequencing, reset, or interrupt functions in multi-rail systems.

For engineers reviewing the MAX6871ETJ+ datasheet, MAX6871ETJ+ pinout, MAX6871ETJ+ application, or MAX6871ETJ+ equivalent, this device supports configurable undervoltage/overvoltage detection, programmable output timing delays (25µs–1600ms), charge-pump outputs for n-FET gate drive, and fault logging - critical for telecom, server, and storage power management validation.

Technical Context

The MAX6871ETJ+ implements a hierarchical digital logic network that maps voltage detector states, GPI inputs, watchdog events, and manual reset signals to five programmable outputs (PO1–PO5) via user-configurable timing blocks and conditional assertion rules. Its internal 10-bit ADC multiplexes across eight analog inputs (IN1–IN4, AUXIN1–AUXIN2, REFIN, DBP) every 200ms, with ±1% total unadjusted error over –40°C to +85°C.

Power is derived either from IN1 (>+6.5V) or the highest of IN3–IN4 (>+2.7V); ABP regulates internal circuitry and supplies charge-pump stages, while DBP powers EEPROM and logic. Thresholds are set in discrete increments: IN1 (25mV/50mV), IN2 (±25mV/±50mV), IN3–IN4 (10mV/20mV), enabling precise margining and dual-fault detection.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Detectors	Four configurable inputs (IN1, IN2, IN3, IN4) with dual thresholds for UV/OV or dual-UV detection - enables robust rail monitoring in complex power trees.
Programmable Outputs	Five outputs (PO1–PO5), each configurable as active-high/low, open-drain, weak pullup, push-pull, or charge-pump - supports flexible reset, enable, or FET-drive signaling.
Timing Delay Range	25µs to 1600ms per output - allows precise sequencing intervals between power rails or subsystems without external timers.
ADC Resolution & Accuracy	10-bit SAR ADC with ±1% total unadjusted error (FSR), monitoring all voltage detectors and two auxiliary inputs - enables real-time telemetry and margin verification.
Interface Protocol	I²C/SMBus-compatible serial interface (400kHz max) with A0/A1 addressing - supports up to four devices on one bus for scalable system supervision.
Threshold Accuracy	±1% over –40°C to +85°C - ensures reliable trip points across temperature for production-grade power integrity validation.
Operating Temperature	–40°C to +85°C extended range - qualified for industrial and telecom infrastructure environments.

Pinout & Package

MAX6871ETJ+ uses a 32-pin 7mm × 7mm thin QFN package (T3277-2) with exposed paddle (EP) internally connected to GND. Pin functions are validated per Maxim's official pin description table for MAX6871 (not MAX6870).

Pin/Terminal	Circuit Role	Design Meaning
PO1 (Pin 32)	Programmable Output 1	Configurable active-high/low, open-drain, weak pullup, or charge-pump; pulls low at 10µA when VABP < UVLO - used for primary reset or enable signal.
PO2 (Pin 1)	Programmable Output 2	Same configuration options as PO1; asserts based on programmed logic - often assigned to secondary rail sequencing or watchdog-triggered action.
PO3 (Pin 2)	Programmable Output 3	Push-pull or open-drain (MAX6871 only); sinks 4mA at 0.4V - suitable for driving logic-level enables or optocoupler inputs directly.
PO4 (Pin 3)	Programmable Output 4	Push-pull or open-drain; identical electrical specs to PO3 - provides redundancy or parallel load handling for critical rails.
PO5 (Pin 5)	Programmable Output 5	Push-pull or open-drain; 10mA source capability at 0.8×VIN_ - designed for higher-current enable signals or status indicators.
IN1 (Pin 30)	High-Voltage Detector Input	Accepts +1.25V to +7.625V (25mV steps) or +2.5V to +13.2V (50mV steps) - monitors auxiliary or bias rails beyond standard logic supply ranges.
IN2 (Pin 29)	Bipolar Detector Input	Supports ±1.25V to ±7.625V (25mV) or ±2.5V to ±15.25V (50mV) - enables negative rail supervision in mixed-signal or analog subsystems.
IN3/IN4 (Pins 28/27)	Positive Voltage Inputs	Each configurable from +0.5V to +3.05V (10mV) or +1.0V to +5.5V (20mV) - monitors core, I/O, or memory rails with fine-grained margining.
GPI1–GPI4 (Pins 20–17)	General-Purpose Logic Inputs	Internally pulled to GND via 10µA current sources; programmable as watchdog triggers or output condition modifiers - adds board-level control flexibility.
MR (Pin 12)	Manual Reset Input	Active-low, 1µs minimum pulse width, 100ns glitch rejection - enables hardware-initiated system reset during test or recovery.
MARGIN (Pin 11)	Margin Disable Input	Overrides MR when both asserted; holds outputs in current state during voltage margining tests - essential for production burn-in and validation.
SDA/SCL (Pins 13/14)	I²C Serial Interface	Open-drain, 400kHz compliant, with 10pF input capacitance - connects to host microcontroller for runtime reconfiguration and telemetry readback.
A0/A1 (Pins 15/16)	Device Address Inputs	Select one of four I²C addresses (00–11) - allows stacking multiple MAX6871ETJ+ units on shared bus for hierarchical supervision.
AUXIN1/AUXIN2 (Pins 24/23)	Auxiliary Analog Inputs	High-impedance (≥500kΩ), monitored by ADC but not used for sequencing logic - reserved for non-critical voltage telemetry or thermal sensor readback.
ABP (Pin 21)	Internal Analog Power Supply	Regulated output (≈5.4V when IN1 > +6.5V; max of IN3/IN4 otherwise); bypassed with 1µF ceramic - powers internal analog blocks and charge pumps.
DBP (Pin 22)	Internal Digital Power Supply	Regulated output powering EEPROM and logic; bypassed with 1µF ceramic - isolated from ABP to reduce noise coupling into memory operations.
REFIN (Pin 31)	External Reference Input	Accepts +1.225V to +1.275V reference; overrides internal 1.25V reference for improved ADC accuracy - used when absolute measurement fidelity is required.
GND (Pin 4)	Ground Reference	Primary return path for analog and digital circuits; EP (exposed paddle) tied internally to GND - critical for thermal dissipation and noise immunity.

Key Features

Feature	Design Value
EEPROM-based configuration	User-programmable sequencing logic, thresholds, and timing stored in nonvolatile memory - eliminates external configuration components and enables field updates.
Charge-pump output stage (PO1–PO2)	Generates up to VABP + 5V output swing - drives n-channel MOSFET gates directly for high-side power-switching without external level shifters.
Fault register with event logging	Records cause of each output assertion (UV, OV, MR, watchdog timeout) - accelerates root-cause analysis during system failure or qualification testing.
Dual watchdog timers	Independently programmable timeouts (6.25ms–102.4s); clearable by GPI inputs or outputs - supports fail-safe monitoring of processors, FPGAs, or peripheral controllers.
4kb user EEPROM	100,000 erase/write cycles, 10-year data retention - stores calibration data, board IDs, or firmware metadata alongside supervision configuration.

Applications

Telecom Power Management	Server Board Sequencing
Use Scenario: Monitoring +12V bias, –48V line, +3.3V core, and +1.8V I/O rails in central office line cards with automatic failover and telemetry reporting. IC Role / Device Role / Timing Role: Sequencer/supervisor managing power-up order, detecting undervoltage on –48V line, asserting reset if IN2 falls below –44V, and logging fault to host via I²C. Use Value: Prevents latch-up during brownout by halting sequencing until all rails stabilize; ±1% threshold accuracy ensures compliance with GR-1089-CORE immunity requirements.	Use Scenario: Coordinating startup of CPU VDD, memory VDDQ, PCIe slot power, and BMC supply in dual-socket servers with tight timing windows. IC Role / Device Role / Timing Role: Supervisor asserting PO1 after 100ms delay once +1.8V rail reaches threshold, then enabling PO2 after additional 50ms for DDR4 termination voltage. Use Value: Eliminates need for discrete RC timers and comparators; programmable delays ensure JEDEC-compliant power-on reset timing without layout changes.
Storage Controller Supervision	Industrial Baseband Unit
Use Scenario: Validating +5V SATA power, +3.3V NVMe controller, +1.2V FPGA core, and +1.0V PHY rails in enterprise SSD modules under thermal stress. IC Role / Device Role / Timing Role: ADC continuously samples IN3–IN4 and AUXIN1 every 200ms; fault register logs transient dropout on +1.2V rail exceeding 100µs duration. Use Value: Enables predictive maintenance via voltage trend analysis; 10mV threshold resolution detects early regulator degradation before functional failure.	Use Scenario: Managing power sequencing for RF transceiver ASIC, ADC/DAC bias supplies, and FPGA configuration in 5G small-cell baseband units. IC Role / Device Role / Timing Role: Using GPI1 as watchdog input from FPGA; if unrefreshed for 25ms, PO3 asserts to cycle power to transceiver ASIC via charge-pump-driven FET. Use Value: Provides autonomous recovery from lockup without host intervention; charge-pump output eliminates need for isolated DC-DC for gate drive.

Telecom Power Management

Server Board Sequencing

Use Scenario: Monitoring +12V bias, –48V line, +3.3V core, and +1.8V I/O rails in central office line cards with automatic failover and telemetry reporting.

IC Role / Device Role / Timing Role: Sequencer/supervisor managing power-up order, detecting undervoltage on –48V line, asserting reset if IN2 falls below –44V, and logging fault to host via I²C.

Use Value: Prevents latch-up during brownout by halting sequencing until all rails stabilize; ±1% threshold accuracy ensures compliance with GR-1089-CORE immunity requirements.

Use Scenario: Coordinating startup of CPU VDD, memory VDDQ, PCIe slot power, and BMC supply in dual-socket servers with tight timing windows.

IC Role / Device Role / Timing Role: Supervisor asserting PO1 after 100ms delay once +1.8V rail reaches threshold, then enabling PO2 after additional 50ms for DDR4 termination voltage.

Use Value: Eliminates need for discrete RC timers and comparators; programmable delays ensure JEDEC-compliant power-on reset timing without layout changes.

Storage Controller Supervision

Industrial Baseband Unit

Use Scenario: Validating +5V SATA power, +3.3V NVMe controller, +1.2V FPGA core, and +1.0V PHY rails in enterprise SSD modules under thermal stress.

IC Role / Device Role / Timing Role: ADC continuously samples IN3–IN4 and AUXIN1 every 200ms; fault register logs transient dropout on +1.2V rail exceeding 100µs duration.

Use Value: Enables predictive maintenance via voltage trend analysis; 10mV threshold resolution detects early regulator degradation before functional failure.

Use Scenario: Managing power sequencing for RF transceiver ASIC, ADC/DAC bias supplies, and FPGA configuration in 5G small-cell baseband units.

IC Role / Device Role / Timing Role: Using GPI1 as watchdog input from FPGA; if unrefreshed for 25ms, PO3 asserts to cycle power to transceiver ASIC via charge-pump-driven FET.

Use Value: Provides autonomous recovery from lockup without host intervention; charge-pump output eliminates need for isolated DC-DC for gate drive.

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply sequencing/supervision applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX6870ETJ+	Six voltage inputs (IN1–IN6), eight programmable outputs (PO1–PO8), no PO3/PO4 push-pull mode - larger footprint and higher pin count.	Required where six-rail monitoring or eight-output sequencing is needed; not drop-in compatible due to different pin mapping and output count.	Select MAX6870ETJ+ only when full six-input/four-auxiliary-channel capability is required; MAX6871ETJ+ reduces BOM cost and layout complexity for four-input designs.
TPS65988DKR	USB-C PD controller with integrated sequencer; supports USB PD 3.0, CC logic, and 5V/20V VBUS switching - lacks bipolar input, ADC, and SMBus telemetry.	Targeted at USB-C powered devices (dock, monitor, laptop); not suitable for telecom or server multi-rail supervision due to missing IN2/auxiliary monitoring.	Choose TPS65988DKR for USB-C endpoint power negotiation; MAX6871ETJ+ remains preferred for general-purpose, non-USB, high-accuracy multi-rail sequencing with diagnostics.

Compared with MAX6870ETJ+, the MAX6871ETJ+ reduces input count and output count while retaining identical ADC accuracy, threshold resolution, and I²C interface - optimizing cost and PCB area for four-rail systems. Against TPS65988DKR, it offers broader voltage range support, bipolar detection, and embedded telemetry but no USB-C protocol stack.

Availability

MAX6871ETJ+ is available at Aetrix Electronics and suitable for telecommunications infrastructure, server motherboard design, and enterprise storage equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for MAX6871ETJ+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for demanding industrial, automotive, and communications applications.

The MAX6871ETJ+ belongs to Maxim's EEPROM-programmable power-supply sequencer/supervisor family, engineered specifically for high-reliability, multi-rail power management in telecom, server, and storage systems where configurability, accuracy, and diagnostic capability are critical.

FAQ

What is the maximum number of voltage inputs supported by the MAX6871ETJ+?

The MAX6871ETJ+ supports four dedicated voltage detector inputs: IN1 (high-voltage), IN2 (bipolar), and IN3–IN4 (positive-only). Unlike the MAX6870ETJ+, it does not include IN5 or IN6 pins - confirmed by the pin configuration table and ordering information specifying "four voltage detector inputs" for MAX6871. This makes MAX6871ETJ+ ideal for compact four-rail systems.

Does the MAX6871ETJ+ support both undervoltage and overvoltage detection on the same input?

Yes, the MAX6871ETJ+ supports dual-threshold configuration per voltage input, enabling independent undervoltage and overvoltage detection. For example, IN3 can be set to assert an output if voltage drops below 1.75V (UV) or rises above 1.85V (OV), using its 10mV or 20mV step resolution - a capability explicitly documented in the General Description and Electrical Characteristics sections.

Can the MAX6871ETJ+ drive n-channel MOSFETs directly without external level-shifting components?

Yes, the MAX6871ETJ+ PO1 and PO2 outputs support charge-pump mode, generating up to VABP + 5V (e.g., ~10.4V when ABP = 5.4V). This allows direct gate drive of n-channel FETs used in high-side power switches - verified in the Detailed Description section and Figure 9 ("FET turn-on with charge pump") of the datasheet.

What is the accuracy and update rate of the internal ADC in the MAX6871ETJ+?

The MAX6871ETJ+ features a 10-bit ADC with ±1% total unadjusted error over –40°C to +85°C. It monitors all eight analog inputs (IN1–IN4, AUXIN1–AUXIN2, REFIN, DBP) in sequence, completing a full cycle every 200ms - as specified in the Electrical Characteristics table under "ADC Total Monitoring Cycle Time (tC)".

Is the MAX6871ETJ+ pin-compatible with the MAX6870ETJ+?

No, the MAX6871ETJ+ is not pin-compatible with the MAX6870ETJ+. While both use the same 32-pin thin QFN package (T3277-2), their pin assignments differ significantly: MAX6871 omits PO6–PO8 and IN5–IN6, repurposes Pins 6–8 as N.C., and assigns PO3–PO5 to Pins 2–5 instead of Pins 5–7. The official Pin Description table confirms distinct MAX6870/MAX6871 column mappings.

MAX6871ETJ+ Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: -

Package/Case:: 32-WFQFN Exposed Pad

Packaging:: Bulk

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Sequencer

Number of Voltages Monitored:: 4

Voltage - Threshold:: 5 Adjustable Threshold Voltages

Output:: Open Drain, Push-Pull

Reset:: Active High/Active Low

Reset Timeout:: Adjustable/Selectable

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-TQFN (5x5)

MAX6871ETJ+ FAQ

1.How can I place an order for MAX6871ETJ+ through Aetrix?

Please submit a Request for Quotation (RFQ) for MAX6871ETJ+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MAX6871ETJ+ reliable?

The price and inventory of MAX6871ETJ+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6871ETJ+ is usually 5 days.

3.What payment methods are accepted for MAX6871ETJ+?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6871ETJ+ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MAX6871ETJ+?

MAX6871ETJ+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MAX6871ETJ+ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MAX6871ETJ+?

For technical support, including MAX6871ETJ+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6871ETJ+ requirements.

6.How does Aetrix verify that MAX6871ETJ+ is sourced from the original manufacturer or authorized distributors?

All MAX6871ETJ+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6871ETJ+ meets industry standards.

7.What is the process for return or replacement of MAX6871ETJ+?

All MAX6871ETJ+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX6871ETJ+, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MAX6871ETJ+ part is unused and in its original packaging.

Return procedure for MAX6871ETJ+:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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