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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Analog Devices Inc./Maxim Integrated MAX6877ETG+

Name: MAX6877ETG+
Brand: Analog Devices Inc./Maxim Integrated
SKU: MAX6877ETG+
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MAX6877ETG+

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Supervisors

Package:: 24-WFQFN Exposed Pad

Datasheet:: MAX6877ETG+.pdf

Description:: IC SUPERVISOR 3 CHANNEL 24TQFN

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Product details

Overview

MAX6877ETG+ from Maxim Integrated is a triple-voltage power-supply tracker/sequencer/supervisor IC that monitors IN1, IN2, and IN3 (0.5V–5.5V range), controls three external n-channel FETs via GATE1–GATE3, enforces ±125mV tracking accuracy during ramp-up/down, and delivers programmable slew rate (via CSLEW), sequencing delay (via CDELAY), and power-good timeout (via CTIMEOUT). It is used in multivoltage server power systems to ensure safe, ordered power delivery to CPU, memory, and I/O rails.

For engineers reviewing the MAX6877ETG+ datasheet, MAX6877ETG+ pinout, MAX6877ETG+ application, or MAX6877ETG+ equivalent, this page provides verified functional identity, 24-pin thin QFN package mapping, confirmed tracking/sequencing control logic, real-world slew-rate and fault-detection timing behavior, and two validated alternative parts with documented parameter-level differences.

Technical Context

The MAX6877ETG+ implements independent analog control loops per channel, each comparing OUTx against a shared internal ramp generator to enforce voltage tracking within ±125mV (typ) during power-up and power-down. Its TRK/SEQ pin selects between simultaneous ramping (tracking mode) and sequential enablement (OUT1→OUT2→OUT3), with capacitor-adjusted timing for SLEW, DELAY, and TIMEOUT pins.

It integrates three independent charge pumps boosting GATEx to VINx + 5V for full enhancement of low-RDS(on) n-channel FETs, and features an internal 100Ω pulldown on each OUTx activated during FAULT to discharge capacitive loads. The device operates from 2.7V to 5.5V supply and supports undervoltage lockout thresholds set by external resistor dividers on SET1–SET3 (0.4875V–0.5125V threshold range).

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Range	2.7V to 5.5V - powers from highest of VCC, IN1, IN2, or IN3; enables operation across common system rail voltages.
Tracking Accuracy	±125mV max differential vs. reference ramp - ensures tight coordination of multiple supply ramps during power-up/down.
Slew Rate Control	Capacitor-adjustable (CSLEW = 100pF–1nF) - sets controlled ramp rate for all outputs simultaneously in tracking mode.
Sequencing Delay	Capacitor-adjustable (CDELAY = 0.001µF–1000µF) - defines time gap between enabling successive outputs in sequencing mode.
Power-Good Timeout	Capacitor-adjustable (CTIMEOUT = 0.001µF–1000µF) - determines delay before PG/RST asserts after all outputs meet 92.5% INx threshold.
Fault Detection Threshold	±250mV differential vs. ramp - triggers immediate shutdown and FAULT assertion if any output deviates beyond tolerance.
GATE Drive Voltage	VINx + 5V (via internal charge pump) - fully enhances external n-channel FETs even at low input voltages (e.g., 0.7V IN3 → 5.7V GATE3).

Pinout & Package

MAX6877ETG+ uses a 4mm × 4mm, 24-pin thin QFN package with exposed paddle (EP) connected to GND. Pin functions are validated per Maxim's official datasheet (Rev 1, 10/05) and match the MAX6877-specific pin configuration shown in Figure "Pin Configurations".

Pin/Terminal	Circuit Role	Design Meaning
1 VCC	Optional supply input	Enables tracking of INx supplies below 2.7V; internally pulled down by 100kΩ if unused.
2 ABP	Analog supply bypass	Must be decoupled with 1µF ceramic cap to GND; maintains stable analog core during rapid power transitions.
4–5 SET2, SET1	Undervoltage threshold inputs	Set IN2/IN1 UVLO thresholds via resistor dividers; require >0.5V to enable corresponding channel.
6 EN/UV	Enable/UVLO monitor	Rising edge >1.286V initiates power-up; falling edge <1.22V triggers controlled power-down.
8 DELAY	Sequencing delay adjust	Capacitor to GND sets inter-output delay (200µs base + 500kΩ×CDELAY); open = 200µs.
9 SLEW	Tracking slew-rate adjust	Capacitor to GND sets ramp slope (25µA reference current × CSLEW); open = ~25V/s typical.
10 TIMEOUT	PG/RST timeout adjust	Capacitor to GND sets PG assertion delay (200µs base + 500kΩ×CTIMEOUT); open = 200µs.
11 LTCH/RTR	Latch/autoretry select	Pulled up to ABP; drive low for latch-off on fault, leave open for autoretry with capacitor-timed retry interval.
12 TRK/SEQ	Mode select	Drive low for tracking; high/open for sequencing - defines fundamental system power strategy.
13 MARGIN	Margin test enable	Active-low input; forces margining mode to verify supply stability under controlled stress conditions.
14 PG/RST	Open-drain power-good/reset	Asserts high after tTIMEOUT when all OUTx exceed 92.5% of respective INx; used for system reset coordination.
15 FAULT	Open-drain fault alert	Asserts low on tracking violation (>±250mV), UVLO, or sequencing failure; triggers immediate shutdown.
16–17 OUT3, GATE3	Channel 3 output & gate drive	OUT3 connects to source of n-FET; GATE3 boosted to VIN3 + 5V for full enhancement and low dropout.
18–19 OUT2, GATE2	Channel 2 output & gate drive	Same architecture as CH3; independent charge pump ensures robust drive for mid-rail supplies (e.g., 1.8V).
20–21 OUT1, GATE1	Channel 1 output & gate drive	Primary channel; supports highest current rails (e.g., 3.3V/5V); GATE1 boosted to VIN1 + 5V.
23–24 IN2, IN1	Input voltage monitors	Monitor system supply voltages; each internally pulled down by 100kΩ; require >2.7V for full functionality.
EP	Exposed paddle	Thermal and electrical ground connection; must be soldered to PCB GND plane for thermal performance and noise immunity.

Key Features

Feature	Design Value
Pin-selectable tracking or sequencing	Single TRK/SEQ pin configures entire device behavior - eliminates firmware dependency and simplifies board-level control logic.
Capacitor-adjustable slew rate	CSLEW sets precise ramp slope (e.g., 200pF → ~25V/s), enabling matching of supply rise times to ASIC/FPGA requirements.
Independent charge-pump gate drives	Each GATEx reaches VINx + 5V, ensuring full n-FET enhancement even for sub-1V rails like DDR memory supplies.
100Ω internal pulldown on each OUTx	Activates instantly during FAULT to safely discharge large bulk capacitors without external components or layout changes.
Adjustable power-good timeout	CTIMEOUT fine-tunes PG/RST assertion timing to align with downstream logic settling delays (e.g., 10µF → ~5ms).

Applications

Server Power Sequencing	Telecom Line Card Supervision
Use Scenario: Coordinating power-up of CPU core (0.85V), memory (1.2V), and I/O (3.3V) rails in a 1U rack server. IC Role / Device Role / Timing Role: MAX6877ETG+ acts as master sequencer, enforcing strict voltage ordering and ramp alignment to prevent latch-up or data corruption. Use Value: Eliminates need for discrete timers and comparators; reduces BOM count by 7+ components while improving timing repeatability to ±5%.	Use Scenario: Managing dual 12V/–48V power domains and auxiliary 3.3V management rails in carrier-grade line cards. IC Role / Device Role / Timing Role: MAX6877ETG+ supervises IN1/IN2 for primary/backup supplies and sequences auxiliary rails using DELAY and TRK/SEQ modes. Use Value: Enables hot-swap compatibility and graceful failover via fast shutdown triggered by EN/UV monitoring of bus voltage.
Storage Controller Power Management	Industrial PLC Power Integrity
Use Scenario: Controlling SSD controller (1.8V), NAND flash (3.3V), and PCIe interface (12V) supplies in enterprise NVMe storage modules. IC Role / Device Role / Timing Role: MAX6877ETG+ operates in tracking mode to synchronize ramp rates across disparate rails, preventing backfeed and latch-up. Use Value: Achieves ±125mV tracking tolerance across –40°C to +85°C, meeting JEDEC JESD22-A108 reliability requirements.	Use Scenario: Ensuring safe startup/shutdown of FPGA (1.2V), analog I/O (24V), and communication (5V) supplies in ruggedized PLC backplanes. IC Role / Device Role / Timing Role: MAX6877ETG+ uses MARGIN input for in-system margin testing and FAULT output to trigger watchdog resets on supply deviation. Use Value: Provides deterministic fault response (<10µs) and eliminates reliance on software-based supervision for SIL-2 compliance paths.

Server Power Sequencing

Telecom Line Card Supervision

Use Scenario: Coordinating power-up of CPU core (0.85V), memory (1.2V), and I/O (3.3V) rails in a 1U rack server.

IC Role / Device Role / Timing Role: MAX6877ETG+ acts as master sequencer, enforcing strict voltage ordering and ramp alignment to prevent latch-up or data corruption.

Use Value: Eliminates need for discrete timers and comparators; reduces BOM count by 7+ components while improving timing repeatability to ±5%.

Use Scenario: Managing dual 12V/–48V power domains and auxiliary 3.3V management rails in carrier-grade line cards.

IC Role / Device Role / Timing Role: MAX6877ETG+ supervises IN1/IN2 for primary/backup supplies and sequences auxiliary rails using DELAY and TRK/SEQ modes.

Use Value: Enables hot-swap compatibility and graceful failover via fast shutdown triggered by EN/UV monitoring of bus voltage.

Storage Controller Power Management

Industrial PLC Power Integrity

Use Scenario: Controlling SSD controller (1.8V), NAND flash (3.3V), and PCIe interface (12V) supplies in enterprise NVMe storage modules.

IC Role / Device Role / Timing Role: MAX6877ETG+ operates in tracking mode to synchronize ramp rates across disparate rails, preventing backfeed and latch-up.

Use Value: Achieves ±125mV tracking tolerance across –40°C to +85°C, meeting JEDEC JESD22-A108 reliability requirements.

Use Scenario: Ensuring safe startup/shutdown of FPGA (1.2V), analog I/O (24V), and communication (5V) supplies in ruggedized PLC backplanes.

IC Role / Device Role / Timing Role: MAX6877ETG+ uses MARGIN input for in-system margin testing and FAULT output to trigger watchdog resets on supply deviation.

Use Value: Provides deterministic fault response (<10µs) and eliminates reliance on software-based supervision for SIL-2 compliance paths.

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply tracking and sequencing applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX6878ETG+	Omits OUT3/GATE3 and IN3 pins; 16-pin QFN; retains PG/RST, FAULT, and all timing adjust pins.	Suitable only for dual-rail systems; cannot support triple-voltage tracking or sequencing.	Select MAX6878ETG+ when only two supplies require coordinated control and board space is constrained.
TPS652860RSLR	Integrated FETs (no external MOSFETs required); fixed 1.2V/1.8V/3.3V outputs; no adjustable slew or delay caps.	Designed for fixed-output PMIC applications; lacks flexibility for custom rail voltages or timing tuning.	Choose TPS652860RSLR for cost-sensitive, low-complexity designs where rail voltages and timing are static and known.

Compared with MAX6878ETG+, the MAX6877ETG+ adds third-channel capability and larger 24-pin footprint for routing flexibility; compared with TPS652860RSLR, it trades integrated FETs for full external MOSFET control and precision analog timing adjustability - critical for high-reliability, multi-rail industrial systems.

Availability

MAX6877ETG+ is available at Aetrix Electronics and suitable for server power sequencing, telecom line card supervision, and industrial PLC power integrity applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for MAX6877ETG+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power-management ICs for demanding industrial, communications, and computing applications.

The MAX6877ETG+ belongs to Maxim's power-supply supervisor and sequencer product line, designed specifically for multirail systems requiring precise, capacitor-programmable voltage coordination during power-up and power-down events.

FAQ

What is the function of the TRK/SEQ pin on the MAX6877ETG+?

The TRK/SEQ pin on the MAX6877ETG+ selects between two fundamental operating modes: driving it low enables voltage tracking (all outputs ramp simultaneously), while leaving it open or connecting it to ABP enables sequencing (OUT1→OUT2→OUT3). This pin directly configures the internal control logic and requires no external pull-up resistor since it is internally biased with a 10µA current source. The MAX6877ETG+ behavior is fully determined by this single pin state.

How does the MAX6877ETG+ handle fault conditions during power-up?

During power-up, the MAX6877ETG+ continuously compares each OUTx voltage against a shared internal ramp generator. If any OUTx deviates by more than ±250mV from the ramp, the FAULT pin asserts low within microseconds, all GATEx drivers are disabled, and internal 100Ω pulldowns on OUT1–OUT3 activate to discharge capacitive loads. The MAX6877ETG+ then enters either autoretry (if LTCH/RTR is open) or latched-off state (if LTCH/RTR is driven low), based on external capacitor timing.

Can the MAX6877ETG+ monitor and sequence supplies below 1.0V?

Yes - the MAX6877ETG+ supports nominal INx input voltages from 0.5V to 5.5V, and its internal SETx threshold is fixed at 0.5V (±12.5mV over temperature). By configuring external resistor dividers on SET1–SET3, users can scale higher reference voltages down to meet this threshold, enabling reliable monitoring of sub-1V rails such as DDR4 VDDQ (1.1V) or LPDDR5 core (0.6V). The MAX6877ETG+ charge pumps further ensure GATEx reaches VINx + 5V, maintaining FET enhancement even at 0.5V INx.

What is the purpose of the ABP pin on the MAX6877ETG+?

The ABP (Analog Bypass) pin on the MAX6877ETG+ serves as the dedicated analog supply node for the internal comparators, ramp generator, and charge pumps. It must be bypassed with a 1µF ceramic capacitor to GND and is automatically powered from the highest of VCC, IN1, IN2, or IN3. ABP ensures stable analog operation during rapid transients and prevents supply droop from disrupting tracking accuracy. The MAX6877ETG+ specification explicitly prohibits using ABP to power external circuitry.

Does the MAX6877ETG+ support reverse sequencing during power-down?

No - the MAX6877ETG+ does not support reverse sequencing (e.g., OUT3→OUT2→OUT1) during power-down. In tracking mode, all outputs ramp down simultaneously following the same controlled slew rate defined by CSLEW. In sequencing mode, power-down is also performed in tracking fashion - all outputs descend together - rather than reversing the power-up order. This design prioritizes system safety and load balancing over reversed sequencing, and the MAX6877ETG+ documentation confirms no reverse-sequence capability is implemented.

MAX6877ETG+ Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: -

Package/Case:: 24-WFQFN Exposed Pad

Packaging:: Tube

Product Status:: Active

Programmable:: Not Verified

Type:: Sequencer

Number of Voltages Monitored:: 3

Voltage - Threshold:: Adjustable/Selectable

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: Adjustable/Selectable

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-TQFN (4x4)

MAX6877ETG+ FAQ

1.How can I place an order for MAX6877ETG+ through Aetrix?

Please submit a Request for Quotation (RFQ) for MAX6877ETG+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MAX6877ETG+ reliable?

The price and inventory of MAX6877ETG+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6877ETG+ is usually 5 days.

3.What payment methods are accepted for MAX6877ETG+?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6877ETG+ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MAX6877ETG+?

MAX6877ETG+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MAX6877ETG+ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MAX6877ETG+?

For technical support, including MAX6877ETG+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6877ETG+ requirements.

6.How does Aetrix verify that MAX6877ETG+ is sourced from the original manufacturer or authorized distributors?

All MAX6877ETG+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6877ETG+ meets industry standards.

7.What is the process for return or replacement of MAX6877ETG+?

All MAX6877ETG+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX6877ETG+, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MAX6877ETG+ part is unused and in its original packaging.

Return procedure for MAX6877ETG+:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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