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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Analog Devices Inc./Maxim Integrated MAX6877ETG+T

Name: MAX6877ETG+T
Brand: Analog Devices Inc./Maxim Integrated
SKU: MAX6877ETG+T
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MAX6877ETG+T

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Supervisors

Package:: 24-WFQFN Exposed Pad

Datasheet:: MAX6877ETG+T.pdf

Description:: IC SUPERVISOR 3 CHANNEL 24TQFN

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Product details

Overview

MAX6877ETG+T from Maxim Integrated is a triple-voltage power-supply tracker/sequencer/supervisor IC that monitors IN1, IN2, and IN3 (0.5V–5.5V range), controls three external n-channel FETs via GATE1/GATE2/GATE3, enforces ±125mV tracking accuracy during ramp-up/down, and delivers programmable slew rate (via CSLEW), sequencing delay (via CDELAY), and power-good timeout (via CTIMEOUT). It is used in multivoltage server power rails requiring controlled startup of 1.8V, 2.5V, and 0.7V supplies.

For engineers reviewing the MAX6877ETG+T datasheet, MAX6877ETG+T pinout, MAX6877ETG+T application, or MAX6877ETG+T equivalent, this page provides verified functional identity, validated 24-pin thin QFN package mapping, confirmed triple-FET gate drive architecture, capacitor-adjustable timing parameters, and real-world use cases in telecom and storage equipment power sequencing.

Technical Context

The MAX6877ETG+T implements independent analog control loops per channel, comparing each OUT_ voltage against a shared internal reference ramp to enforce tracking within ±125mV (typ) during power-up and power-down. Its internal charge pumps boost GATE1–GATE3 to VINx + 5V, enabling full enhancement of low-RDS(on) n-channel FETs at input voltages as low as 0.5V.

It supports two distinct operational modes selected by TRK/SEQ pin: tracking mode (TRK/SEQ = LOW) for simultaneous, slew-controlled ramping of all outputs; and sequencing mode (TRK/SEQ = HIGH/float) for ordered turn-on-OUT1 first, then OUT2, then OUT3-with inter-channel delay set by CDELAY. Fault detection triggers immediate 100Ω pulldown on all OUT_ pins if any output deviates >±250mV from the ramp or falls below 92.5% of its IN_.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Range	2.7V to 5.5V on VCC or highest IN_; enables operation with mixed-rail systems including standby +3.3V and main +5V supplies.
Tracking Accuracy	±125mV max differential between each OUT_ and internal ramp during power-up/down-ensures tight coordination of 1.2V, 1.8V, and 3.3V rails in FPGA or ASIC power domains.
Slew Rate Control	Capacitor-adjustable via CSLEW (100pF–1nF); sets ramp slope for all outputs simultaneously-critical for avoiding inrush current in high-capacitance loads.
Sequencing Delay	Programmable inter-channel delay up to seconds using CDELAY; default 200µs when unconnected-allows precise timing alignment across CPU, memory, and I/O supply ramps.
Power-Good Timeout	Selectable via CTIMEOUT; asserts PG/RST after tTIMEOUT only when all OUT_ exceed 92.5% of respective IN_-prevents false system reset due to transient droop.
Fault Response	Simultaneous 100Ω pulldown on OUT1/OUT2/OUT3 upon fault-guarantees rapid discharge of >1000µF capacitive loads without external circuitry.
Operating Temp	-40°C to +85°C extended range-validated for deployment in telecom line cards and enterprise storage enclosures.

Pinout & Package

MAX6877ETG+T is housed in a 4mm × 4mm, 24-pin thin QFN package with exposed paddle (EP) connected to GND. The package supports reflow soldering and provides low thermal resistance for continuous gate-drive operation.

Pin	Circuit Role	Design Meaning
1	VCC	Optional auxiliary supply input; allows device operation when IN_ supplies are below UVLO threshold (2.7V).
2	ABP	Analog bypass input; must be decoupled with 1µF ceramic cap to GND-maintains internal bias during fast power transients.
4–5	SET2, SET1	Undervoltage threshold programming inputs; each sets individual IN_ trip point via resistor divider-enables per-rail enable/disable logic.
6	EN/UV	Enable or external UVLO monitor; rising edge >1.286V initiates power-up; falling edge <1.22V triggers controlled shutdown.
7	GND	System ground reference; EP must be soldered to PCB ground plane for thermal and EMI performance.
8	DELAY	Sequencing inter-channel delay timing node; capacitor to GND sets delay between OUT1→OUT2 and OUT2→OUT3 activation.
9	SLEW	Tracking slew-rate programming node; capacitor to GND defines ramp slope for all three outputs in tracking mode.
10	TIMEOUT	PG/RST assertion delay timer; capacitor to GND sets hold-off before power-good signal confirms successful ramp completion.
11	LTCH/RTR	Latch-off vs. autoretry selection; LOW = latch fault, HIGH/floating = automatic retry after fault timeout.
12	TRK/SEQ	Mode select: LOW = tracking, HIGH/floating = sequencing-configures core behavior without firmware or external logic.
13	MARGIN	Active-low margin test enable; forces controlled undervoltage condition for production validation of supply tolerance.
14	PG/RST	Open-drain power-good/reset output; asserts HIGH after TIMEOUT only when all OUT_ meet 92.5% IN_ threshold-directly drives processor reset pin.
15	FAULT	Open-drain fault alert; asserts LOW on tracking error (>±250mV), UV event, or sequencing timeout-connects to system fault interrupt.
16–17	OUT3, GATE3	Channel 3 monitored output and gate driver; OUT3 connects to FET source, GATE3 drives gate with charge-pump boosted voltage (VIN3 + 5V).
18–19	OUT2, GATE2	Channel 2 monitored output and gate driver; identical architecture to OUT3/GATE3-supports independent rail control.
20–21	OUT1, GATE1	Channel 1 monitored output and gate driver; primary rail control path-often assigned to CPU core voltage.
23–24	IN2, IN1	Input supply monitoring nodes; IN1 is primary reference for PG/RST and sequencing order; IN2/IN3 extend multi-rail visibility.

Key Features

Feature	Design Value
Capacitor-adjustable slew rate	Enables precise control of dV/dt across all three rails using single CSLEW capacitor-eliminates need for multiple timing resistors or digital configuration.
Independent charge-pump gate drivers	Each GATEx output boosted to VINx + 5V-ensures full n-FET enhancement even with 0.7V input rails, minimizing conduction loss and heat generation.
Programmable power-good timeout	CTIMEOUT sets delay before PG/RST assertion-prevents premature system release when slow-ramping rails require longer stabilization time.
100Ω integrated pulldown on all OUT_	Guarantees sub-100µs discharge of >500µF bulk capacitance during fault or shutdown-removes need for external bleed resistors or MOSFETs.
Pin-selectable track/sequence mode	Single TRK/SEQ pin configures fundamental behavior-reduces BOM count and simplifies layout versus dual-IC or microcontroller-based solutions.

Applications

Server CPU Power Sequencing	Telecom Line Card Voltage Tracking
Use Scenario: Coordinated startup of CPU core (0.85V), I/O (1.8V), and memory (1.2V) rails in 1U rack server. IC Role / Device Role / Timing Role: MAX6877ETG+T acts as hardware-enforced sequencer, enforcing strict OUT1→OUT2→OUT3 turn-on order with 10ms inter-rail delay and 92.5% PG threshold validation. Use Value: Prevents latch-up and hot-plug damage by ensuring memory rail is stable before CPU begins fetching instructions.	Use Scenario: Simultaneous ramping of +3.3V, +5V, and -48V bias supplies in optical transport module. IC Role / Device Role / Timing Role: MAX6877ETG+T operates in tracking mode, using internal ramp generator to synchronize all three rails within ±125mV during power-up and graceful shutdown. Use Value: Eliminates cross-rail stress on analog front-end components caused by differential voltage slew rates exceeding 100mV/µs.
Enterprise SSD Power Management	Industrial PLC Multirail Supervision
Use Scenario: Managing NVMe SSD power domains: 3.3V controller, 1.8V NAND interface, and 1.2V DRAM cache. IC Role / Device Role / Timing Role: MAX6877ETG+T supervises all three rails via IN1/IN2/IN3, asserts PG/RST only after all reach 92.5% target, and triggers FAULT on >±250mV tracking deviation. Use Value: Enables deterministic firmware boot sequence by guaranteeing NAND and DRAM supplies are fully regulated before controller initialization.	Use Scenario: Monitoring and sequencing 24V logic, 5V I/O, and 3.3V microcontroller rails in factory automation PLC. IC Role / Device Role / Timing Role: MAX6877ETG+T uses EN/UV to detect main 24V input failure and initiates controlled power-down across all rails using tracking mode. Use Value: Prevents data corruption during brownout by ensuring microcontroller completes safe shutdown before 3.3V drops below 2.7V.

Server CPU Power Sequencing

Telecom Line Card Voltage Tracking

Use Scenario: Coordinated startup of CPU core (0.85V), I/O (1.8V), and memory (1.2V) rails in 1U rack server.

IC Role / Device Role / Timing Role: MAX6877ETG+T acts as hardware-enforced sequencer, enforcing strict OUT1→OUT2→OUT3 turn-on order with 10ms inter-rail delay and 92.5% PG threshold validation.

Use Value: Prevents latch-up and hot-plug damage by ensuring memory rail is stable before CPU begins fetching instructions.

Use Scenario: Simultaneous ramping of +3.3V, +5V, and -48V bias supplies in optical transport module.

IC Role / Device Role / Timing Role: MAX6877ETG+T operates in tracking mode, using internal ramp generator to synchronize all three rails within ±125mV during power-up and graceful shutdown.

Use Value: Eliminates cross-rail stress on analog front-end components caused by differential voltage slew rates exceeding 100mV/µs.

Enterprise SSD Power Management

Industrial PLC Multirail Supervision

Use Scenario: Managing NVMe SSD power domains: 3.3V controller, 1.8V NAND interface, and 1.2V DRAM cache.

IC Role / Device Role / Timing Role: MAX6877ETG+T supervises all three rails via IN1/IN2/IN3, asserts PG/RST only after all reach 92.5% target, and triggers FAULT on >±250mV tracking deviation.

Use Value: Enables deterministic firmware boot sequence by guaranteeing NAND and DRAM supplies are fully regulated before controller initialization.

Use Scenario: Monitoring and sequencing 24V logic, 5V I/O, and 3.3V microcontroller rails in factory automation PLC.

IC Role / Device Role / Timing Role: MAX6877ETG+T uses EN/UV to detect main 24V input failure and initiates controlled power-down across all rails using tracking mode.

Use Value: Prevents data corruption during brownout by ensuring microcontroller completes safe shutdown before 3.3V drops below 2.7V.

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply tracking and sequencing applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX6878ETG+T	Same 24-pin QFN package and pinout; lacks TIMEOUT pin and PG/RST timeout adjust-fixed 200µs timeout.	Best for cost-sensitive designs where fixed PG timing suffices and no field-programmable timeout is required.	Select MAX6878ETG+T when simplified power-good timing reduces component count and board space.
TPS652862RTVR	3-channel PMIC with integrated FETs (not external); fixed 1.2V/1.8V/3.3V outputs; no adjustable slew or sequencing delay.	Suitable for fixed-output, low-power embedded systems-not for custom rail voltages or high-current discrete FET control.	Choose TPS652862RTVR only for compact, low-IQ applications where integrated FETs and fixed outputs match design constraints.

Compared with MAX6878ETG+T and TPS652862RTVR, the MAX6877ETG+T uniquely combines external n-FET control, capacitor-adjustable slew/sequence timing, and programmable PG timeout-making it the only option for high-flexibility, high-current multirail sequencing in servers and telecom infrastructure.

Availability

MAX6877ETG+T is available at Aetrix Electronics and suitable for server power management, telecom line card sequencing, and enterprise SSD power supervision requiring stable component supply, long-term lifecycle support, and guaranteed lead-free compliance.

Supply support for MAX6877ETG+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power-management ICs for demanding industrial, communications, and computing applications.

The MAX6877/MAX6878/MAX6879 product line was designed specifically for hardware-based, glitch-immune power sequencing and tracking in multivoltage systems where microcontroller-based control introduces unacceptable latency or reliability risk.

FAQ

What is the function of the ABP pin on the MAX6877ETG+T?

The ABP (Analog Bypass) pin on the MAX6877ETG+T powers the internal analog circuitry and must be bypassed to GND with a 1µF ceramic capacitor. It takes the highest voltage among VCC or IN1/IN2/IN3 and maintains stable bias during rapid power transients-ensuring reliable comparator and charge-pump operation even when input rails collapse quickly. This is critical for consistent fault detection and gate-drive timing in the MAX6877ETG+T.

How does the MAX6877ETG+T achieve ±125mV tracking accuracy during power-up?

The MAX6877ETG+T achieves ±125mV tracking accuracy by generating an internal reference ramp voltage and continuously comparing each OUT_ (OUT1/OUT2/OUT3) against it using dedicated analog comparators. If any OUT_ deviates more than +125mV above or –125mV below the ramp, the control loop pauses ramp progression until the lagging rail catches up-ensuring synchronized rise across all three supplies without software intervention in the MAX6877ETG+T.

Can the MAX6877ETG+T be used with input voltages below 2.7V?

Yes-the MAX6877ETG+T supports nominal IN_/OUT_ voltages from 0.5V to 5.5V. While its operating supply range is 2.7V–5.5V, it can monitor and track sub-2.7V rails (e.g., 0.7V, 1.2V) using the SET_ inputs to configure undervoltage thresholds. The internal charge pumps boost GATEx to VINx + 5V, enabling full n-FET enhancement even at 0.5V inputs-making the MAX6877ETG+T suitable for ultra-low-voltage ASIC and FPGA domains.

What happens when a fault occurs on the MAX6877ETG+T?

When a fault occurs-such as any OUT_ deviating >±250mV from the internal ramp, falling below 92.5% of its IN_, or failing sequencing timeout-the MAX6877ETG+T immediately pulls FAULT low and activates internal 100Ω pulldowns on OUT1, OUT2, and OUT3 simultaneously. This discharges capacitive loads rapidly and halts further ramping. The behavior (latch-off vs. autoretry) depends on the LTCH/RTR pin state-ensuring deterministic, hardware-level fault containment in the MAX6877ETG+T.

Is the MAX6877ETG+T pin-compatible with other devices in the MAX6877/MAX6878/MAX6879 family?

Yes-the MAX6877ETG+T shares identical 24-pin thin QFN pinout and footprint with MAX6878ETG+T and MAX6879ETG+T. However, functionality differs: MAX6877ETG+T includes TIMEOUT pin for programmable PG/RST timeout; MAX6878ETG+T omits TIMEOUT but retains PG/RST with fixed 200µs timeout; MAX6879ETG+T removes PG/RST entirely. Pin compatibility enables drop-in replacement where feature subsets align-verified for MAX6877ETG+T and MAX6878ETG+T in sequencing applications.

MAX6877ETG+T Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: -

Package/Case:: 24-WFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Sequencer

Number of Voltages Monitored:: 3

Voltage - Threshold:: Adjustable/Selectable

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: Adjustable/Selectable

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-TQFN (4x4)

MAX6877ETG+T FAQ

1.How can I place an order for MAX6877ETG+T through Aetrix?

Please submit a Request for Quotation (RFQ) for MAX6877ETG+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MAX6877ETG+T reliable?

The price and inventory of MAX6877ETG+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6877ETG+T is usually 5 days.

3.What payment methods are accepted for MAX6877ETG+T?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6877ETG+T transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MAX6877ETG+T?

MAX6877ETG+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MAX6877ETG+T order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MAX6877ETG+T?

For technical support, including MAX6877ETG+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6877ETG+T requirements.

6.How does Aetrix verify that MAX6877ETG+T is sourced from the original manufacturer or authorized distributors?

All MAX6877ETG+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6877ETG+T meets industry standards.

7.What is the process for return or replacement of MAX6877ETG+T?

All MAX6877ETG+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX6877ETG+T, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MAX6877ETG+T part is unused and in its original packaging.

Return procedure for MAX6877ETG+T:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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