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Analog Devices Inc./Maxim Integrated MAX6878ETG+T
- Part No.:
- MAX6878ETG+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
MAX6878ETG+T.pdf
- Description:
- IC SUPERVISOR 2 CHANNEL 24TQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,456
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Product details
Overview
MAX6878ETG+T from Maxim Integrated is a triple-voltage power-supply tracker/sequencer/supervisor that monitors IN1, IN2, and IN3 (0.5V–5.5V), controls three external n-channel FETs via GATE1/GATE2/GATE3, enforces ±125mV tracking accuracy during ramp-up/down, supports capacitor-adjustable slew rate (via SLEW pin), and delivers power-good signaling with selectable timeout (via TIMEOUT pin) for system reset coordination in multivoltage server and telecom power rails.
For engineers reviewing the MAX6878ETG+T datasheet, MAX6878ETG+T pinout, MAX6878ETG+T application, or MAX6878ETG+T equivalent, this device is selected when precise voltage tracking (±125mV), programmable sequencing delay (via DELAY), fault-protected shutdown with 100Ω pulldown, internal charge-pump gate drive (VIN + 5V), and dual-mode TRK/SEQ configuration are required for high-reliability 3-rail power management.
Technical Context
The MAX6878ETG+T implements analog control-loop tracking using an internally generated reference ramp voltage compared against each OUT_ via dedicated comparators; tracking error is continuously monitored to halt ramp progression if any OUT_ deviates >±125mV from the ramp, and fault assertion occurs at >±250mV. It supports two distinct operational modes: tracking (TRK/SEQ = low) for simultaneous, slew-controlled ramping of all outputs, and sequencing (TRK/SEQ = high/unconnected) for ordered turn-on (OUT1→OUT2→OUT3) with per-channel delay set by CDELAY.
Power delivery relies on independent internal charge pumps boosting GATE1/GATE2/GATE3 to VINx + 5V - enabling full enhancement of low-RDS(on) n-channel FETs even with sub-1V input rails - while ABP bypassed with 1µF maintains analog supply stability during fast transients. Fault response includes simultaneous 100Ω pulldown activation across all OUT_ pins and open-drain FAULT assertion within programmable tFAULT.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Input Range | IN1/IN2/IN3: 0.5V to 5.5V; VCC optional; device powers from highest of IN_/VCC ≥2.7V |
| Tracking Accuracy | ±125mV max differential between each OUT_ and internal ramp during power-up/down |
| Slew Rate Control | Capacitor-adjustable via SLEW pin (CSLEW = 100pF–1nF); typical 25µA reference current |
| Sequencing Delay | Capacitor-adjustable via DELAY pin (CDELAY); default 200µs, extended to ms range |
| Power-Good Timeout | Capacitor-adjustable via TIMEOUT pin (CTIMEOUT); default 200µs, scalable to milliseconds |
| Fault Response | 100Ω internal pulldown activated on all OUT_ pins during FAULT assertion |
| Gate Drive Voltage | GATE1/GATE2/GATE3 boosted to VINx + 5V via independent charge pumps |
Pinout & Package
MAX6878ETG+T is housed in a 4mm × 4mm, 24-pin thin QFN package with exposed paddle (EP) connected to GND. Pin count and layout match the MAX6877ETG+ but exclude SET3 and TIMEOUT functions - confirming MAX6878ETG+T as the 24-pin variant supporting PG/RST timeout adjustment and dual-tracking/sequencing mode selection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 1) | Optional auxiliary supply input | Enables operation when IN_ < 2.7V; internally pulled down with 100kΩ |
| ABP (Pin 2) | Analog supply bypass | Must be decoupled with 1µF ceramic to GND; powers analog core during transients |
| SET1/SET2 (Pins 5/4) | IN1/IN2 undervoltage threshold adjust | Resistor-divider sets 0.5V threshold; all SET_ > 0.5V required to enable tracking/sequencing |
| EN/UV (Pin 6) | Enable or UVLO monitor input | Rising edge >1.286V enables power-up; falling edge <1.22V initiates controlled power-down |
| DELAY (Pin 8) | Sequencing startup delay control | Capacitor to GND sets delay before OUT1 turn-on or inter-channel gap in sequencing mode |
| SLEW (Pin 9) | Tracking slew-rate control | Capacitor to GND sets ramp slope for simultaneous OUT1/OUT2/OUT3 voltage rise/fall |
| TIMEOUT (Pin 10) | PG/RST timeout period adjust | Capacitor to GND sets delay after all OUT_ meet VTH_PG before PG/RST asserts high |
| LTCH/RTR (Pin 11) | Latch vs. autoretry mode select | Pulled up internally; drive low for latch-off on fault, leave open for autoretry |
| TRK/SEQ (Pin 12) | Mode selection input | Drive low for tracking; high/unconnected for sequencing (internally pulled up) |
| MARGIN (Pin 13) | Active-low margin test enable | Drives low to force OUT_ to 90% of IN_ for production margin testing |
| PG/RST (Pin 14) | Open-drain power-good/reset output | Asserts high tTIMEOUT after all OUT_ exceed 92.5% of respective IN_ voltages |
| FAULT (Pin 15) | Open-drain fault alert output | Asserts low if tracking error >±250mV, any OUT_ < IN_, or fault persists beyond tFAULT |
| OUT1/OUT2/OUT3 (Pins 20/18/16) | Monitored output voltage sense points | Connected to source of external n-channel FETs; each has 100Ω pulldown during fault |
| GATE1/GATE2/GATE3 (Pins 21/19/17) | Gate drive outputs | Charge-pump boosted to VINx + 5V to fully enhance n-FETs with minimal RDS(on) |
| IN1/IN2/IN3 (Pins 24/23/22) | Input supply voltage monitoring inputs | Each internally pulled down with 100kΩ; must exceed VABP = 2.7V for full functionality |
| GND (Pin 7) | Ground reference | Primary return path for analog/digital circuitry and pulldown networks |
| EP | Exposed thermal paddle | Must be soldered to PCB ground plane for thermal dissipation and EMI reduction |
Key Features
| Feature | Design Value |
|---|---|
| Capacitor-adjustable tracking slew rate | Enables precise control of voltage ramp time across all three rails using single CSLEW capacitor |
| Independent charge-pump gate drivers | Delivers VINx + 5V to each GATE pin, ensuring full n-FET enhancement even with 0.7V IN3 rail |
| Programmable power-good timeout | Allows system designers to align PG/RST assertion timing with downstream load stabilization requirements |
| 100Ω integrated pulldown on each OUT_ | Guarantees rapid discharge of capacitive loads during fault or shutdown without external components |
| Pin-selectable tracking or sequencing mode | Single TRK/SEQ pin configures entire device behavior - no firmware or register writes required |
| Adjustable undervoltage lockout per rail | SET1/SET2 resistor dividers allow independent UVLO thresholds for IN1 and IN2 (IN3 disabled on MAX6878) |
Applications
| Server Power Sequencing | Telecom Line Card Supervision |
|---|---|
Use Scenario: Coordinated startup of CPU core (0.85V), I/O (1.8V), and memory (1.2V) rails in enterprise servers to prevent latch-up or inrush damage. IC Role / Device Role / Timing Role: MAX6878ETG+T acts as hardware-based sequencer enforcing OUT1→OUT2→OUT3 order with programmable inter-rail delays and PG/RST confirmation. Use Value: Eliminates need for FPGA-based sequencing logic; reduces BOM count by integrating timing, supervision, and gate drive into one 4mm×4mm IC. |
Use Scenario: Monitoring and controlled ramp-down of +3.3V, +5V, and -48V bias supplies in optical line cards during hot-swap events. IC Role / Device Role / Timing Role: MAX6878ETG+T operates in tracking mode to ensure all rails decay synchronously within ±125mV during graceful shutdown. Use Value: Prevents reverse current flow and data corruption by maintaining voltage ordering during power removal - verified by FAULT pin deassertion only when all rails cross safe thresholds. |
| Network Switch ASIC Power Management | Industrial PLC Dual-Rail Control |
Use Scenario: Managing power-up of 12nm ASIC core (0.75V) and auxiliary (1.1V) supplies where tight tracking prevents electromigration and thermal stress. IC Role / Device Role / Timing Role: MAX6878ETG+T serves as precision tracker with CSLEW-tuned ramp rate, comparing each OUT_ to common internal ramp in real time. Use Value: Achieves ±125mV tracking tolerance across temperature (-40°C to +85°C), exceeding typical ASIC vendor requirements without calibration. |
Use Scenario: Controlling isolated 24V field power and 5V logic rails in programmable logic controllers where fault isolation is critical. IC Role / Device Role / Timing Role: MAX6878ETG+T uses EN/UV to initiate sequencing, MARGIN for production test, and FAULT to trigger safety cutoff relays. Use Value: Integrates functional safety elements (autoretry/latch mode, 100Ω pulldowns, open-drain alerts) into single component - reducing certification effort for IEC 61508 SIL2 systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power-supply tracking and sequencing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6877ETG+T | 24-pin QFN with identical pinout; includes TIMEOUT pin but lacks SET3 - same tracking/sequencing capability as MAX6878ETG+T | No functional difference in dual-rail use cases; both support IN1/IN2 tracking and sequencing with PG/RST timeout | Select MAX6877ETG+T only if board layout already accommodates TIMEOUT function; otherwise MAX6878ETG+T offers identical performance with optimized feature set |
| TPS65286RTVR | 3-channel PMIC with integrated FETs (not external); fixed 0.5%/ms slew; no capacitor-adjustable timing; supports I²C configuration | Better for space-constrained designs needing integration; unsuitable where external high-current n-FETs or custom slew/timeout are required | Choose TPS65286RTVR for compact, low-power applications without need for external FET control; MAX6878ETG+T remains preferred for high-current, flexible, hardware-configured systems |
Compared with MAX6877ETG+T, the MAX6878ETG+T provides identical dual-rail tracking/sequencing capability in the same 24-pin package but omits unused SET3 - simplifying design-in. Against TPS65286RTVR, MAX6878ETG+T trades integration for flexibility: external FET selection, capacitor-programmable timing, and hardware-only configuration eliminate firmware dependencies and support higher current rails.
Availability
MAX6878ETG+T is available at Aetrix Electronics and suitable for server power sequencing, telecom line card supervision, and industrial PLC dual-rail control requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for mission-critical deployments.
Supply support for MAX6878ETG+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power-management ICs for demanding industrial, communications, and computing applications.
The MAX6878ETG+T belongs to Maxim's multivoltage power-supply supervisor family, engineered specifically for hardware-configured, high-reliability tracking and sequencing of up to three independent rails in servers, networking gear, and telecom infrastructure.
FAQ
What is the maximum number of voltage rails the MAX6878ETG+T can manage?
The MAX6878ETG+T monitors and controls exactly two independent voltage rails: IN1/OUT1 and IN2/OUT2. Although physically packaged in a 24-pin QFN shared with the triple-rail MAX6877/MAX6879, the MAX6878ETG+T does not support IN3/OUT3 functionality - its SET3, TIMEOUT, and IN3 pins are unconnected internally. This makes it a purpose-optimized dual-rail solution with full feature parity for those two channels, including adjustable slew, sequencing delay, and power-good timeout.
How does the MAX6878ETG+T achieve accurate voltage tracking without external op-amps or DACs?
The MAX6878ETG+T achieves ±125mV tracking accuracy using an internal analog control loop: it generates a precision reference ramp voltage and compares each OUT_ (via dedicated comparator blocks) to that ramp in real time. If any OUT_ deviates more than +125mV or –125mV, the ramp halts until the slowest rail catches up. This closed-loop analog architecture - implemented entirely within the MAX6878ETG+T die - eliminates dependency on external components while maintaining performance across –40°C to +85°C.
Can the MAX6878ETG+T be used in systems with sub-1V input supplies?
Yes - the MAX6878ETG+T supports IN1 and IN2 as low as 0.5V, and its internal charge pumps boost GATE1 and GATE2 to VINx + 5V. This allows full enhancement of standard n-channel MOSFETs even when driving 0.7V or 0.85V rails, achieving low RDS(on) and minimal dropout. Operation requires only that ABP (powered from the highest IN_/VCC) remains ≥2.7V - a condition easily met when one rail is ≥2.7V or VCC is supplied externally.
What happens during a fault condition on the MAX6878ETG+T?
Upon fault detection - such as any OUT_ deviating >±250mV from the tracking ramp, falling below its IN_ voltage, or failing to meet VTH_PG - the MAX6878ETG+T immediately pulls FAULT low (open-drain), disables all GATE outputs, and activates 100Ω pulldowns on OUT1, OUT2, and OUT3 to rapidly discharge capacitive loads. Behavior after fault depends on LTCH/RTR: if driven low, latching occurs; if left open, autoretry initiates after tRETRY (capacitor-adjustable via SLEW pin).
Is the MAX6878ETG+T pin-compatible with other devices in the MAX6877/MAX6878/MAX6879 family?
Yes - the MAX6878ETG+T shares the identical 24-pin thin QFN (4mm × 4mm) pinout with the MAX6877ETG+T, including matching assignments for VCC, ABP, SET1, SET2, EN/UV, DELAY, SLEW, TIMEOUT, TRK/SEQ, PG/RST, FAULT, OUT1/OUT2, GATE1/GATE2, IN1/IN2, and GND. However, MAX6878ETG+T leaves SET3, IN3, and associated pins (e.g., Pin 3, 22) unconnected internally - making it a drop-in replacement for MAX6877ETG+T in dual-rail designs where TIMEOUT functionality is retained but SET3/IN3 are unused.
MAX6878ETG+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 2
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TQFN (4x4)
MAX6878ETG+T FAQ
1.How can I place an order for MAX6878ETG+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX6878ETG+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX6878ETG+T reliable?
The price and inventory of MAX6878ETG+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6878ETG+T is usually 5 days.
3.What payment methods are accepted for MAX6878ETG+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6878ETG+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX6878ETG+T?
MAX6878ETG+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX6878ETG+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX6878ETG+T?
For technical support, including MAX6878ETG+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6878ETG+T requirements.
6.How does Aetrix verify that MAX6878ETG+T is sourced from the original manufacturer or authorized distributors?
All MAX6878ETG+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6878ETG+T meets industry standards.
7.What is the process for return or replacement of MAX6878ETG+T?
All MAX6878ETG+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX6878ETG+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX6878ETG+T part is unused and in its original packaging.
Return procedure for MAX6878ETG+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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