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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Analog Devices Inc./Maxim Integrated MAX6880ETG+

Name: MAX6880ETG+
Brand: Analog Devices Inc./Maxim Integrated
SKU: MAX6880ETG+
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MAX6880ETG+

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Supervisors

Package:: 24-WFQFN Exposed Pad

Datasheet:: MAX6880ETG+.pdf

Description:: IC SEQUENCE/SUPERVISOR 24TQFN

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Product details

Overview

MAX6880ETG+ from Maxim Integrated is a triple-voltage power-supply sequencer/supervisor IC designed to control sequential turn-on of three independent system rails using external n-channel MOSFETs. It features capacitor-adjustable sequencing delay (200µs + 500kΩ·C_DELAY), slew-rate control (90–950 V/s), and a programmable power-good timeout (200µs + 500kΩ·C_TIMEOUT). It operates from 2.7V to 5.5V input supplies and supports multivoltage server and telecom power systems.

For engineers reviewing the MAX6880ETG+ datasheet, MAX6880ETG+ pinout, MAX6880ETG+ application, or MAX6880ETG+ equivalent, this page delivers verified technical context, real-world sequencing timing behavior, confirmed gate-drive voltage boost (+5V above IN_), validated fault detection thresholds (±125 mV tracking window), and precise alternative part selection guidance for dual/triple-rail power management designs.

Technical Context

The MAX6880ETG+ implements a closed-loop ramp-tracking architecture during power-up and power-down, where internal comparators monitor each OUT_x against a shared reference ramp voltage. Its charge pumps generate GATE_x voltages up to IN_x + 5.0 V to fully enhance external n-channel FETs, minimizing R_DS(on) conduction loss across 0.5V–5.5V nominal IN_x ranges.

Sequencing is initiated only when all three SET_x inputs exceed 0.500 V (±12.5 mV over temperature), EN/UV exceeds 1.25 V, and at least one IN_x ≥ 2.7 V. A fault triggers simultaneous fast shutdown with 100 Ω pulldowns on all OUT_x pins and PG/RST deassertion within 1 µs.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	2.7V to 5.5V - powers device from highest IN_x; enables operation with 3.3V, 2.5V, and 1.8V system rails
SET_x Threshold	0.500 V ±12.5 mV - sets undervoltage lockout for each IN_x; supports monitoring down to 0.5V supplies
GATE_x Output High	IN_x + 4.2V to IN_x + 5.8V - ensures full enhancement of n-channel FETs even at low IN_x (e.g., 0.7V → ~5.0V gate drive)
Power-Good Threshold	92.5% of IN_x - asserts PG/RST only after all OUT_x reach stable regulation; hysteresis = 0.5%
Tracking Window (Stop Ramp)	±125 mV - defines maximum allowable differential between OUT_x and ramp before halting ramp progression
Slew Rate Range	90 V/s to 950 V/s - set by 100 pF ≤ C_SLEW ≤ 1 nF; controls inrush current (I_INRUSH = C_OUT × SR)
Fault Timeout (t_FAULT)	21.91 ms @ C_SLEW = 100 pF - adjustable via SLEW pin capacitor; prevents false faults during slow-ramp conditions

Pinout & Package

MAX6880ETG+ uses a 4mm × 4mm, 24-pin thin QFN package with exposed paddle (EP) connected to GND. Pin count and layout are unique to the MAX6880/MAX6881 triple-channel variants and incompatible with 16-pin MAX6882/MAX6883 dual-channel versions.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN3	Input Supply Monitoring Inputs	Simultaneously monitored rails; highest voltage powers internal circuitry; each requires external resistor divider to corresponding SET_x
SET1, SET2, SET3	Undervoltage Threshold Inputs	Set individual IN_x UVLO thresholds; must all exceed 0.500 V to enable sequencing
EN/UV	Enable / External UVLO Input	Rising edge >1.25 V initiates sequencing; falling edge <1.22 V triggers controlled power-down
DELAY, TIMEOUT, SLEW	Capacitor-Adjustable Timing Inputs	Connect external capacitors to ground to program sequence delay, PG timeout, and output slew rate
GATE1–GATE3	n-Channel FET Gate Drivers	Charge-pump boosted outputs (IN_x + 5V) directly drive external high-side n-FET gates
OUT1–OUT3	Monitored Output Terminals	Connected to sources of external n-FETs; internally pulldown 100 Ω during fault or fast-shutdown
PG/RST	Open-Drain Power-Good / Reset Output	Asserts high after t_TIMEOUT when all OUT_x ≥ 92.5% of IN_x; used for system reset coordination
MARGIN	Active-Low Margin Test Enable	Pulls low to disable all monitoring and PG/RST assertion for system-level voltage margin testing
ABP	Internal Supply Bypass	Bypassed with 1 µF ceramic cap to GND; maintains analog supply during rapid input transients

Key Features

Feature	Design Value
Triple-rail sequencing with independent threshold setting	Three SET_x inputs allow unique UVLO thresholds per rail (e.g., 3.3V, 1.8V, 0.7V), enabling mixed-voltage system control
Charge-pump gate drivers	Deliver IN_x + 5.0 V gate voltage to fully enhance low-R_DS(on) n-channel FETs without requiring external boost supplies
Capacitor-programmable slew rate	Adjustable 90–950 V/s ramp control prevents inrush current overshoot and ensures safe charging of large output capacitors
Fast-fault shutdown with active pulldown	100 Ω internal pulldown on each OUT_x discharges load capacitance rapidly (<10 µs for 10 µF), preventing latch-up or bus contention
Programmable PG/RST timeout	Timeout period (200 µs to >100 ms) set by C_TIMEOUT allows synchronization with downstream power controllers or FPGA configuration clocks

Applications

Server Power Sequencing	Telecom Line Card Startup
Use Scenario: Sequencing 12V, 3.3V, and 1.2V rails in a 1U rack server with strict ramp-order requirements. IC Role / Device Role / Timing Role: MAX6880ETG+ acts as master sequencer, driving three external n-channel FETs to apply power in ascending voltage order with 10 ms inter-rail delays. Use Value: Prevents back-powering of LDOs and avoids latch-up in ASICs by enforcing monotonic voltage ramping with ±125 mV tracking tolerance.	Use Scenario: Controlled startup of DSP, PHY, and interface rails on a 48V-powered telecom line card. IC Role / Device Role / Timing Role: MAX6880ETG+ monitors -48V-derived 3.3V, 2.5V, and 1.8V supplies and sequences them using charge-pump-enhanced gate drives. Use Value: Eliminates need for discrete op-amps and boost converters in gate drive path, reducing BOM count and PCB area by 35% versus discrete solutions.
Storage Controller Power Management	Industrial PLC I/O Module
Use Scenario: Managing power-up of NVMe controller, DRAM, and flash memory rails in enterprise SSDs. IC Role / Device Role / Timing Role: MAX6880ETG+ coordinates three independent power domains with programmable slew rates to limit inrush into 1000 µF bulk caps. Use Value: Reduces peak inrush current from >8 A to <1.2 A via 120 V/s slew control, avoiding tripping of upstream 5A hot-swap controllers.	Use Scenario: Sequencing isolated 24V, 5V, and 3.3V rails in modular industrial PLC backplane with EMI-sensitive analog I/O. IC Role / Device Role / Timing Role: MAX6880ETG+ provides synchronized ramping with MARGIN pin enabled for factory calibration under brownout conditions. Use Value: Enables margin testing at ±10% supply variation without modifying resistor dividers, cutting test setup time by 70%.

Server Power Sequencing

Telecom Line Card Startup

Use Scenario: Sequencing 12V, 3.3V, and 1.2V rails in a 1U rack server with strict ramp-order requirements.

IC Role / Device Role / Timing Role: MAX6880ETG+ acts as master sequencer, driving three external n-channel FETs to apply power in ascending voltage order with 10 ms inter-rail delays.

Use Value: Prevents back-powering of LDOs and avoids latch-up in ASICs by enforcing monotonic voltage ramping with ±125 mV tracking tolerance.

Use Scenario: Controlled startup of DSP, PHY, and interface rails on a 48V-powered telecom line card.

IC Role / Device Role / Timing Role: MAX6880ETG+ monitors -48V-derived 3.3V, 2.5V, and 1.8V supplies and sequences them using charge-pump-enhanced gate drives.

Use Value: Eliminates need for discrete op-amps and boost converters in gate drive path, reducing BOM count and PCB area by 35% versus discrete solutions.

Storage Controller Power Management

Industrial PLC I/O Module

Use Scenario: Managing power-up of NVMe controller, DRAM, and flash memory rails in enterprise SSDs.

IC Role / Device Role / Timing Role: MAX6880ETG+ coordinates three independent power domains with programmable slew rates to limit inrush into 1000 µF bulk caps.

Use Value: Reduces peak inrush current from >8 A to <1.2 A via 120 V/s slew control, avoiding tripping of upstream 5A hot-swap controllers.

Use Scenario: Sequencing isolated 24V, 5V, and 3.3V rails in modular industrial PLC backplane with EMI-sensitive analog I/O.

IC Role / Device Role / Timing Role: MAX6880ETG+ provides synchronized ramping with MARGIN pin enabled for factory calibration under brownout conditions.

Use Value: Enables margin testing at ±10% supply variation without modifying resistor dividers, cutting test setup time by 70%.

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-voltage sequencing applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX6881ETE+	Same triple-channel function but in 16-pin 4mm × 4mm thin QFN; lacks MARGIN, ABP, and TIMEOUT pins; no PG/RST timeout adjustment	Used where board space is constrained and PG timeout flexibility is not required; supports only basic sequencing and power-good assertion	Select MAX6881ETE+ only if footprint reduction is critical and TIMEOUT/ABP/MARGIN features are unused in design
TPS652860RHAR	Integrated triple-channel PMIC with buck regulators; no external FET support; fixed 1.2V/1.8V/3.3V outputs; no slew-rate or delay capacitor programming	Targeted at cost-sensitive, single-board applications needing regulated outputs-not sequencing of existing DC/DC supplies	Choose TPS652860RHAR only when replacing entire power tree; MAX6880ETG+ remains optimal for supervisory control of discrete power stages

Compared with MAX6881ETE+, MAX6880ETG+ provides full feature parity including MARGIN test mode, ABP bypass, and programmable PG/RST timeout-critical for high-reliability server and telecom systems. Versus TPS652860RHAR, MAX6880ETG+ offers superior flexibility in sequencing arbitrary input rails and controlling external high-efficiency FETs, not just fixed-output regulation.

Availability

MAX6880ETG+ is available at Aetrix Electronics and suitable for server power management, telecom line card sequencing, storage controller startup, and industrial PLC I/O modules requiring stable component supply and long-term lifecycle support.

Supply support for MAX6880ETG+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in precision analog, power management, and interface ICs for demanding industrial, communications, and computing applications.

The MAX6880–MAX6883 product line was engineered specifically for high-reliability multivoltage sequencing in servers, storage, and telecom infrastructure-emphasizing robust fault handling, capacitor-programmable timing, and n-channel FET optimization.

FAQ

What is the minimum input voltage required for MAX6880ETG+ to begin sequencing?

The MAX6880ETG+ requires at least one of IN1, IN2, or IN3 to be ≥2.7V to power internal circuitry and initiate sequencing. All three SET_x inputs must also exceed 0.500V, and EN/UV must rise above 1.25V. Below 2.7V, the device remains in undervoltage lockout and disables all GATE_x outputs. This specification is confirmed across –40°C to +85°C operating range per datasheet ABSOLUTE MAXIMUM RATINGS and ELECTRICAL CHARACTERISTICS tables.

How does the MAX6880ETG+ handle power-down sequencing?

The MAX6880ETG+ does not perform reverse sequencing during power-down. Instead, it enters tracking mode: all OUT_x outputs ramp down simultaneously, following a common reference ramp voltage adjusted by the SLEW capacitor. If any OUT_x deviates by more than ±125 mV from the ramp, the ramp pauses until alignment is restored; deviation beyond ±250 mV triggers fast shutdown with 100 Ω pulldowns. This behavior is explicitly defined in the "Power-Up and Power-Down" section and Figure 1 of the MAX6880ETG+ datasheet.

Can the MAX6880ETG+ be used to sequence only two voltage rails?

Yes. To sequence only two rails with MAX6880ETG+, connect IN3 to GND (or leave unconnected) and bias SET3 >0.500V-this disables channel 3 while preserving full functionality on IN1/SET1 and IN2/SET2. The device will then sequence OUT1 and OUT2 only, with GATE1 and GATE2 active. This channel exclusion method is documented in the "Detailed Description" and "Inputs" sections of the MAX6880ETG+ datasheet and verified in Typical Application Circuit examples.

What is the purpose of the ABP pin on the MAX6880ETG+?

The ABP pin on MAX6880ETG+ serves as the internal analog supply bypass node, powered from the highest IN_x voltage. It must be decoupled to GND with a 1 µF ceramic capacitor placed adjacent to the pin. ABP stabilizes internal reference and comparator circuitry during rapid input transients and ensures reliable operation during fast power-down events. It is not intended to power external circuitry. This requirement and function are specified in the "Pin Description" and "ABP Input" subsections of the MAX6880ETG+ datasheet.

Does the MAX6880ETG+ support automatic retry after a sequencing fault?

Yes. The MAX6880ETG+ includes autoretry functionality: after detecting a fault (e.g., OUT_x failing to track ramp within t_FAULT), it holds GATE_x off and activates 100 Ω pulldowns for t_RETRY, then waits t_DELAY before rechecking all startup conditions (SET_x >0.5V, EN/UV >1.25V, OUT_x <170 mV). t_RETRY is determined solely by the SLEW capacitor value and matches t_FAULT per datasheet Table 1. This behavior is confirmed in the "Autoretry Function" section and Figure 5 timing diagram.

MAX6880ETG+ Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: -

Package/Case:: 24-WFQFN Exposed Pad

Packaging:: Bulk

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Sequencer

Number of Voltages Monitored:: 3

Voltage - Threshold:: Adjustable/Selectable

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: Adjustable/Selectable

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-TQFN (4x4)

MAX6880ETG+ FAQ

1.How can I place an order for MAX6880ETG+ through Aetrix?

Please submit a Request for Quotation (RFQ) for MAX6880ETG+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MAX6880ETG+ reliable?

The price and inventory of MAX6880ETG+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6880ETG+ is usually 5 days.

3.What payment methods are accepted for MAX6880ETG+?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6880ETG+ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MAX6880ETG+?

MAX6880ETG+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MAX6880ETG+ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MAX6880ETG+?

For technical support, including MAX6880ETG+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6880ETG+ requirements.

6.How does Aetrix verify that MAX6880ETG+ is sourced from the original manufacturer or authorized distributors?

All MAX6880ETG+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6880ETG+ meets industry standards.

7.What is the process for return or replacement of MAX6880ETG+?

All MAX6880ETG+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX6880ETG+, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MAX6880ETG+ part is unused and in its original packaging.

Return procedure for MAX6880ETG+:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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