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Analog Devices Inc./Maxim Integrated MAX6882ETE+
- Part No.:
- MAX6882ETE+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
MAX6882ETE+.pdf
- Description:
- IC SEQUENCE/SUPERVISOR 16TQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,777
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Product details
Overview
The MAX6882ETE+ from Maxim Integrated is a dual-voltage power-supply sequencer/supervisor designed to control external n-channel MOSFETs for precise, capacitor-adjustable power-up sequencing of two system rails (OUT1 and OUT2). It features internal charge pumps boosting GATE1/GATE2 to IN1+5V/IN2+5V, 92.5% VTH_PG power-good assertion, and 100Ω internal pulldowns for fast fault discharge - used in multivoltage server and telecom power systems.
For engineers reviewing the MAX6882ETE+ datasheet, MAX6882ETE+ pinout, MAX6882ETE+ application, or MAX6882ETE+ equivalent, this page delivers verified sequencing timing parameters, gate-drive voltage headroom, PG/RST timeout configurability, slew-rate control range (90–950 V/s), and confirmed dual-rail supervision architecture - all specific to the MAX6882ETE+ 16-pin thin QFN variant.
Technical Context
The MAX6882ETE+ implements a reference-ramp-based closed-loop sequencing controller that forces OUT1 and OUT2 to track a programmable internal ramp during power-up, with dynamic stop-and-wait behavior if either output lags by more than 125 mV. Its dual-channel architecture excludes IN3/SET3/GATE3/OUT3 pins entirely - confirmed by pin mapping and functional description.
Sequencing is initiated only when both SET1 and SET2 exceed 0.5 V (±12.5 mV over temperature), EN/UV exceeds 1.25 V, and at least one IN_ input is ≥2.7 V. Fault detection triggers simultaneous fast shutdown via 100Ω pulldowns and IGDS >20 mA gate sink current - independent of the MAX6880/MAX6881 triple-channel variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.5 V - powers device from highest IN_ rail; enables operation across standard logic and core supply domains. |
| Power-Good Threshold | 92.5% of IN1/IN2 - ensures stable sequencing completion before asserting PG/RST; hysteresis = 0.5%. |
| GATE Drive Voltage | IN_ + 5 V - internal charge pump fully enhances external n-channel FETs, minimizing RDS(on) and conduction loss. |
| Slew Rate Range | 90 V/s to 950 V/s - set by 100 pF–1 nF capacitor on SLEW pin; directly controls inrush current (IINRUSH = COUT × SR). |
| Sequencing Delay | 200 µs base + 500 kΩ × CDELAY - configurable inter-rail timing; default delay requires no external capacitor. |
| PG/RST Timeout | 200 µs base + 500 kΩ × CTIMEOUT - delays PG high assertion after all outputs stabilize; supports reset timing coordination. |
| Operating Temperature | -40°C to +85°C - qualified for industrial and telecom equipment environments without derating. |
Pinout & Package
MAX6882ETE+ uses a 4 mm × 4 mm, 16-pin thin QFN package with exposed paddle (EP) connected to GND. Pin count and function mapping differ from MAX6880/MAX6881 (24-pin) and exclude all IN3/SET3/GATE3/OUT3 signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 8, 9, 10 | N.C. | No internal connection - unused pins; must be left floating or tied to GND per layout best practice. |
| 2 | ABP | Internal supply bypass - connect 1 µF ceramic cap to GND; maintains analog supply during rapid IN_ collapse. |
| 3, 4 | SET2, SET1 | Undervoltage threshold inputs - set IN2/IN1 UVLO thresholds via resistor dividers; 0.5 V internal reference. |
| 5 | EN/UV | Enable or external UVLO monitor - rising edge >1.25 V initiates sequencing; falling edge <1.22 V triggers tracking power-down. |
| 6 | GND | Ground reference - connects to EP; primary return path for internal charge pumps and pulldowns. |
| 7 | DELAY | Sequencing delay control - capacitor to GND sets time between OUT1 and OUT2 turn-on (min 200 µs). |
| 11 | SLEW | Slew-rate programming - capacitor to GND sets ramp speed (90–950 V/s) and fault timeout (tFAULT = 2.191×10⁸ × CSLEW). |
| 12 | TIMEOUT | PG/RST timeout control - capacitor to GND sets delay before PG high assertion after sequencing success. |
| 13 | MARGIN | Margin test enable - active-low input disables monitoring and PG/RST; allows safe voltage margining below SET thresholds. |
| 14 | PG/RST | Open-drain power-good/reset - asserts high tTIMEOUT after both OUT1/OUT2 exceed 92.5% of IN1/IN2. |
| 15, 16 | OUT2, OUT1 | Monitored output nodes - connect to sources of external n-channel FETs; 100 Ω pulldown activates on fault. |
| 17, 18 | GATE2, GATE1 | Gate drive outputs - charge-pumped to IN2+5 V / IN1+5 V; fully enhance low-RDS(on) FETs for minimal dropout. |
| 19, 20 | IN2, IN1 | Supply input rails - highest voltage powers device; each internally pulled down by 100 kΩ; ≥2.7 V required for operation. |
Key Features
| Feature | Design Value |
|---|---|
| Capacitor-adjustable sequencing delay | Programmable 200 µs base + 500 kΩ × CDELAY - enables precise inter-rail timing without firmware or external timers. |
| Integrated charge-pump gate drivers | GATE1/GATE2 boosted to IN1+5 V / IN2+5 V - eliminates need for external high-side drivers or bootstrap circuits. |
| Configurable power-good timeout | tTIMEOUT = 200 µs + 500 kΩ × CTIMEOUT - decouples PG assertion from sequencing completion for robust system reset timing. |
| Dynamic ramp tracking with stop-and-wait | 125 mV tracking window (VTRK) - prevents sequencing failure when one rail lags; avoids false faults during slow-start supplies. |
| Fault-activated 100 Ω pulldown | Simultaneous 100 Ω discharge on OUT1/OUT2 - ensures rapid capacitive load discharge (<10 µs for 10 µF) during shutdown or fault. |
Applications
| Server Power Sequencing | Telecom Line Card Supply Control |
|---|---|
Use Scenario: Sequencing 12 V, 3.3 V, and 1.8 V rails in a dual-CPU server motherboard where OUT1 controls 12 V to VRMs and OUT2 controls 3.3 V to I/O peripherals. IC Role / Device Role / Timing Role: Dual-channel supervisor enforcing strict power-up order and synchronized power-down tracking with fault-triggered fast discharge. Use Value: Prevents back-powering of downstream regulators and ensures clean state transitions during hot-swap events. |
Use Scenario: Managing redundant 5 V and 3.3 V supplies on a telecom line card where sequencing must tolerate ±10% input tolerance and transient immunity. IC Role / Device Role / Timing Role: Dual-voltage sequencer with 100 mV transient immunity and adjustable slew rate to dampen inrush during field-replaceable unit insertion. Use Value: Eliminates manual sequencing logic and reduces BOM count by replacing discrete timers, comparators, and MOSFET drivers. |
| Industrial PLC Power Management | Networking Switch ASIC Power-Up |
Use Scenario: Controlling isolated 24 V and 5 V rails powering FPGA and analog front-end in an industrial PLC with extended -40°C to +85°C operation. IC Role / Device Role / Timing Role: Dual-rail sequencer with MARGIN input enabling factory calibration mode - allows voltage margin testing without modifying hardware thresholds. Use Value: Supports production test automation and field diagnostics while maintaining full operational integrity during normal use. |
Use Scenario: Enabling 1.2 V core and 1.8 V I/O supplies for a multi-gigabit Ethernet switch ASIC requiring sub-100 ms sequencing with fault recovery. IC Role / Device Role / Timing Role: Dual-channel sequencer with autoretry (tRETRY set by SLEW capacitor) - automatically reattempts power-up after transient brownout. Use Value: Increases system uptime by recovering from brief supply dips without host processor intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-voltage sequencing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6883ETE+ | Identical pinout and package; lacks MARGIN input and ABP pin - simplified variant without margin-test capability. | Not suitable for production test or voltage-margining workflows requiring MARGIN functionality. | Select MAX6882ETE+ when margin testing, ABP bypass stability, or legacy design compatibility is required. |
| TPS65023RGZR | Triple-output PMIC with integrated DC/DC converters; no external FET gate drive; fixed 1.2 V/1.8 V/3.3 V outputs. | Replaces discrete regulator + sequencer combo; not compatible with custom voltage rails or external FETs. | Choose MAX6882ETE+ for flexible rail voltages, external FET selection, and high-current (>5 A) applications beyond PMIC limits. |
Compared with MAX6883ETE+, the MAX6882ETE+ adds MARGIN and ABP for enhanced testability and supply stability; compared with TPS65023RGZR, it provides full external FET control and arbitrary voltage sequencing - critical for high-efficiency, high-current, or non-standard rail configurations.
Availability
MAX6882ETE+ is available at Aetrix Electronics and suitable for server power management, telecom line card sequencing, and industrial PLC power control requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for MAX6882ETE+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power-management ICs for industrial, communications, and computing applications - emphasizing reliability, integration, and thermal performance.
The MAX6880–MAX6883 family targets multivoltage system power sequencing with external FET control, delivering programmable timing, fault resilience, and wide-input operation - specifically optimized for telecom, server, and embedded infrastructure.
FAQ
What is the exact pin configuration difference between MAX6882ETE+ and MAX6880ETG+?
The MAX6882ETE+ uses a 16-pin thin QFN package with pins 1, 8–10, 11, and 12 assigned as N.C., ABP, SET2, SET1, EN/UV, GND, DELAY, SLEW, TIMEOUT, and MARGIN - omitting all IN3/SET3/GATE3/OUT3 signals present in the 24-pin MAX6880ETG+. This reflects its dual-channel-only architecture and confirmed pin mapping in the datasheet's ordering table and pin description section.
Does MAX6882ETE+ support three-rail sequencing like MAX6880ETG+?
No. The MAX6882ETE+ is explicitly a dual-voltage sequencer - it monitors and sequences only IN1/OUT1/GATE1 and IN2/OUT2/GATE2. The datasheet states "MAX6882/MAX6883 sequence two voltages" and confirms absence of IN3, SET3, GATE3, and OUT3 pins in its 16-pin pinout. Three-rail sequencing requires MAX6880ETG+ or MAX6881ETE+.
What is the minimum external capacitor value required on the SLEW pin for stable operation of MAX6882ETE+?
The MAX6882ETE+ requires CSLEW between 100 pF and 1 nF for valid slew-rate control and fault timeout setting. Below 100 pF, parasitic PCB capacitance dominates, causing inaccurate timing; above 1 nF, slew rates fall below 90 V/s and tFAULT exceeds practical limits. The datasheet specifies 100 pF < CSLEW < 1 nF as the validated operating range.
How does the MAX6882ETE+ handle power-down sequencing?
The MAX6882ETE+ performs simultaneous, tracking-based power-down - not reverse sequencing. When EN/UV falls below 1.22 V, OUT1 and OUT2 ramp down together following a common reference ramp. If either output leads by >125 mV, the ramp pauses until alignment; if deviation exceeds 250 mV, a fault triggers fast shutdown with 100 Ω pulldowns and GATEx forced low.
Is the PG/RST output of MAX6882ETE+ open-drain or push-pull?
The PG/RST output of MAX6882ETE+ is open-drain, as explicitly stated in the Pin Description section: "PG/RST - Power-Good Output, Open-Drain." It requires an external pull-up resistor to the desired logic rail (e.g., 3.3 V or 5 V) and sinks current when asserted low during fault or pre-sequence conditions.
MAX6882ETE+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 2
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TQFN (4x4)
MAX6882ETE+ FAQ
1.How can I place an order for MAX6882ETE+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX6882ETE+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX6882ETE+ reliable?
The price and inventory of MAX6882ETE+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6882ETE+ is usually 5 days.
3.What payment methods are accepted for MAX6882ETE+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6882ETE+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX6882ETE+?
MAX6882ETE+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX6882ETE+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX6882ETE+?
For technical support, including MAX6882ETE+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6882ETE+ requirements.
6.How does Aetrix verify that MAX6882ETE+ is sourced from the original manufacturer or authorized distributors?
All MAX6882ETE+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6882ETE+ meets industry standards.
7.What is the process for return or replacement of MAX6882ETE+?
All MAX6882ETE+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX6882ETE+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX6882ETE+ part is unused and in its original packaging.
Return procedure for MAX6882ETE+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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