Analog Devices Inc./Maxim Integrated MAX6889ETJ+C9L
- Part No.:
- MAX6889ETJ+C9L
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
MAX6889ETJ+C9L.pdf
- Description:
- IC SUPERVISOR 8 CHANNEL 32TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
The MAX6889ETJ+C9L from Maxim Integrated is an EEPROM-configurable, octal-input power-supply sequencer/supervisor with ten programmable outputs, ±1% threshold accuracy, and I²C/SMBus interface. It monitors eight voltage inputs (IN1–IN8), supports 25µs–1600ms output timing delays, and operates across –40°C to +85°C for server and telecom power-rail sequencing.
For engineers reviewing the MAX6889ETJ+C9L datasheet, MAX6889ETJ+C9L pinout, MAX6889ETJ+C9L application, or MAX6889ETJ+C9L equivalent, key selection criteria include configurable undervoltage detection thresholds (1.25V–15.25V), watchdog timeout programmability (6.25ms–102.4s), 512-bit user EEPROM endurance (100,000 cycles), and 32-pin thin QFN package compatibility with high-density PCB layouts.
Technical Context
The MAX6889ETJ+C9L implements a dual-domain power architecture: IN1 powers internal circuitry via a 5.4V LDO when ≥6.5V, while IN2–IN5 supply VCC directly otherwise. Its eight voltage detectors feature independent threshold programming in 10mV/25mV/50mV steps, with high-Z mode enabling sub-1V monitoring (0.167V–1.017V) using external dividers.
Each of its ten PO_ outputs is independently configurable as active-high, active-low, open-drain, or weak pullup, with dedicated timing delay blocks (25µs–1600ms) and conditional assertion logic tied to voltage inputs, GPI_, MR, MARGIN, or watchdog events - enabling precise multi-rail power-up/down sequencing without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Count | Eight voltage detector inputs (IN1–IN8) and four general-purpose logic inputs (GPI1–GPI4) |
| Output Count | Ten programmable outputs (PO1–PO10), each configurable as active-high/low, open-drain, or weak pullup |
| Threshold Accuracy | ±1% over temperature for IN2–IN7 at 1V–5.5V; ±1% for IN1/IN8 at 6.25V–13.2V/6.25V–15.25V |
| Timing Delay Range | 25µs to 1600ms per output, set via register-controlled timing blocks for precise sequencing intervals |
| Watchdog Timeout | Independently programmable initial/normal periods from 6.25ms to 102.4s, configurable per GPI_/PO_ trigger condition |
| Interface | SMBus/I²C-compatible 2-wire serial interface (400kHz max) with A0/A1 address pins supporting up to four devices on one bus |
| User EEPROM | 512-bit internal user EEPROM with 100,000 erase/write cycles and 10-year data retention |
Pinout & Package
MAX6889ETJ+C9L is housed in a 32-pin, 5mm × 5mm × 0.8mm thin QFN package with exposed thermal pad (EP), rated for –40°C to +85°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PO1–PO10 | Programmable output stages | Individually configurable as active-high/low, open-drain, or weak pullup; each includes dedicated timing delay block (25µs–1600ms) |
| IN1, IN8 | High-voltage detector inputs | IN1: 1.25V–13.2V (25/50mV steps); IN8: 1.25V–15.25V (25/50mV steps); both support bypass capacitor for noise immunity |
| IN2–IN7 | General voltage detector inputs | IN2–IN7: 0.5V–5.5V (10/20mV steps); IN2–IN5 also serve as primary power sources for internal circuitry |
| GPI1–GPI4 | General-purpose logic inputs | Internally pulled low with 10µA current sink; configurable as watchdog triggers or PO_ control signals |
| MR, MARGIN | System control inputs | MR asserts reset state; MARGIN overrides MR and holds PO_ in existing state; both internally pulled up to DBP (2.55V) |
| SDA, SCL, A0, A1 | I²C/SMBus interface | Open-drain SDA/SCL require external pullups; A0/A1 set device address (up to four MAX6889 on shared bus) |
| VCC, DBP | Internal power rails | VCC: analog supply (bypass with 1µF); DBP: digital/EEPROM supply (2.55V LDO, bypass with 1µF); neither intended for external loading |
| GND, EP | Ground connections | Pin 4, Pin 31, and exposed paddle (EP) are all internally connected to system ground; EP must be soldered to PCB ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Eight configurable voltage detectors | IN1/IN8 support 1.25V–15.25V ranges in fine increments; IN2–IN7 cover 0.5V–5.5V with high-Z mode down to 0.167V |
| Ten independent programmable outputs | Each PO_ has dedicated timing block and logic configuration-no external glue logic required for complex sequencing |
| Configurable watchdog timer | Two independent timeout periods (initial/normal), each programmable from 6.25ms to 102.4s, with flexible trigger conditions |
| On-chip 512-bit user EEPROM | Persistent storage for system-specific calibration data or configuration flags; 100k-cycle endurance ensures field reliability |
| Multi-source power architecture | Auto-selects power from IN1 (≥6.5V), IN2–IN5, or external VCC-eliminates need for auxiliary bias supplies |
Applications
| Server Power Sequencing | Telecom Line Card Supervision |
|---|---|
Use Scenario: Sequencing 12V, 5V, 3.3V, 1.8V, and 1.2V rails in multi-processor server motherboards with strict ramp-time and dependency requirements. IC Role / Device Role / Timing Role: Central sequencer/supervisor that monitors all rail voltages, asserts resets only after valid sequencing order, and manages margining during production test. Use Value: Eliminates discrete RC timers and logic gates; reduces BOM count by >7 components per board while enabling firmware-reconfigurable sequencing. |
Use Scenario: Monitoring redundant 48V DC input, intermediate 12V/5V rails, and FPGA core voltages in carrier-grade line cards with hot-swap capability. IC Role / Device Role / Timing Role: Fault-tolerant supervisor that detects undervoltage on any monitored rail and initiates controlled shutdown via programmable outputs to isolation MOSFETs. Use Value: Achieves <100µs fault response time and supports dual-watchdog configurations for fail-safe operation in NEBS-compliant systems. |
| Storage Controller Power Management | Industrial Multi-Microprocessor Systems |
Use Scenario: Coordinating power-up of NVMe SSD controller, DRAM buffers, and PCIe PHY in enterprise storage enclosures with staggered load requirements. IC Role / Device Role / Timing Role: Sequencer that enforces inter-rail delays (e.g., 10ms between 12V and 3.3V), monitors VDDQ stability before releasing reset, and logs faults to internal EEPROM. Use Value: Enables deterministic boot across heterogeneous storage platforms; internal EEPROM stores last-fault code for field diagnostics without host intervention. |
Use Scenario: Managing independent 3.3V, 2.5V, and 1.2V supplies for ARM, DSP, and FPGA subsystems in programmable logic controllers with isolated I/O domains. IC Role / Device Role / Timing Role: Distributed supervisor where GPI inputs link to safety-critical sensors, and PO outputs drive enable lines for isolated DC-DC converters. Use Value: Supports functional safety requirements via configurable watchdog timeout escalation and margin-disable during maintenance mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power-supply sequencing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6890ETI+ | Six voltage inputs (IN1–IN6), eight programmable outputs, 28-pin QFN; lacks IN7/IN8 and two PO_ outputs | Lower channel count suits compact single-processor systems; no high-voltage IN8 for >13.2V monitoring | Select when sequencing complexity is reduced and board space is constrained; not drop-in due to pin count and function reduction |
| TPS659122ZQW | TI PMIC with integrated DC-DC converters and LDOs; six configurable supervisors but no EEPROM-based configuration storage | Integrated power conversion eliminates external regulators but fixes rail voltages; no field-reprogrammable sequencing logic | Choose for cost-sensitive, fixed-rail designs where integration outweighs configurability; requires full schematic redesign |
Compared with MAX6890ETI+, the MAX6889ETJ+C9L provides two additional voltage inputs and two extra programmable outputs for complex multi-rail systems; versus TPS659122ZQW, it offers field-updatable sequencing logic and higher voltage monitoring flexibility at the expense of integrated regulation.
Availability
MAX6889ETJ+C9L is available at Aetrix Electronics and suitable for server motherboard design, telecom line card development, and industrial embedded control systems requiring stable component supply and long-term lifecycle support.
Supply support for MAX6889ETJ+C9L includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for power management, sensing, and communication applications.
The MAX6889 belongs to Maxim's EEPROM-programmable power-supply sequencer family, engineered specifically for high-reliability, multi-rail sequencing in servers, storage, and telecom infrastructure where firmware-defined timing and fault response are critical.
FAQ
What is the maximum voltage the MAX6889ETJ+C9L can monitor on IN8?
The MAX6889ETJ+C9L supports up to 15.25V on IN8 when configured in 50mV threshold increments, or up to 7.625V in 25mV increments. This high-voltage capability enables direct monitoring of legacy 12V and 15V rails without external level-shifting, and the input withstands up to +20V absolute maximum rating for transient robustness.
How does the MAX6889ETJ+C9L handle power supply during startup when multiple input rails are present?
The MAX6889ETJ+C9L uses a virtual diode-ORing scheme to auto-select power from IN1 (if ≥6.5V), IN2–IN5, or an external VCC. Internal hysteresis prevents supply switching when input voltages are within 50mV, ensuring stable operation during rail ramp-up. The highest valid input powers the internal 5.4V LDO (for IN1) or directly supplies VCC.
Can the MAX6889ETJ+C9L's 512-bit user EEPROM be used to store custom calibration data?
Yes-the MAX6889ETJ+C9L includes a dedicated 512-bit user EEPROM with guaranteed 100,000 erase/write cycles and 10-year data retention. It is accessible via the same I²C/SMBus interface used for configuration registers and is commonly used to store board-specific trim values, fault logs, or manufacturing test results without host processor involvement.
What is the minimum detectable voltage threshold on IN2–IN7 using high-Z mode?
In high-Z mode, the MAX6889ETJ+C9L supports voltage detection from 0.167V to 1.017V on IN2–IN7 using 3.3mV increments. This requires an external resistor divider to scale higher system voltages into this range, enabling precise monitoring of sub-1V FPGA core supplies or ASIC I/O rails with ±1% accuracy maintained across temperature.
Does the MAX6889ETJ+C9L support simultaneous assertion of multiple programmable outputs?
Yes-the MAX6889ETJ+C9L allows any combination of its ten PO_ outputs to be asserted simultaneously based on independent logic conditions (voltage input, GPI_, MR, watchdog, or margin disable). Each output has its own timing delay block and polarity configuration, enabling parallel control of multiple power domains or reset signals without contention.
MAX6889ETJ+C9L Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 8
- Voltage - Threshold:
- 8 Selectable Threshold Combinations
- Output:
- Open Drain, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-TQFN (5x5)
MAX6889ETJ+C9L FAQ
1.How can I place an order for MAX6889ETJ+C9L through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX6889ETJ+C9L on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX6889ETJ+C9L reliable?
The price and inventory of MAX6889ETJ+C9L are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6889ETJ+C9L is usually 5 days.
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Once your MAX6889ETJ+C9L order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX6889ETJ+C9L?
For technical support, including MAX6889ETJ+C9L datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6889ETJ+C9L requirements.
6.How does Aetrix verify that MAX6889ETJ+C9L is sourced from the original manufacturer or authorized distributors?
All MAX6889ETJ+C9L products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6889ETJ+C9L meets industry standards.
7.What is the process for return or replacement of MAX6889ETJ+C9L?
All MAX6889ETJ+C9L units undergo pre-shipment inspection (PSI). If there is an issue with MAX6889ETJ+C9L, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX6889ETJ+C9L part is unused and in its original packaging.
Return procedure for MAX6889ETJ+C9L:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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