Analog Devices Inc./Maxim Integrated MAX6890ETI+
- Part No.:
- MAX6890ETI+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Supervisors
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
MAX6890ETI+.pdf
- Description:
- IC SUPERVISOR 6 CHANNEL 28TQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,622
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
The MAX6890ETI+ from Maxim Integrated is an EEPROM-configurable, six-input voltage supervisor and power-supply sequencer with eight programmable outputs (active-high/low, open-drain, weak pullup), ±1% threshold accuracy, 25µs–1600ms configurable timing delays, and SMBus/I²C interface - used for precise multi-rail sequencing in telecom servers and base stations.
For engineers reviewing the MAX6890ETI+ datasheet, MAX6890ETI+ pinout, MAX6890ETI+ application, or MAX6890ETI+ equivalent, this page delivers verified functional identity, validated pin roles, confirmed sequencing parameters, real-world use cases, and two rigorously cross-checked alternative parts for supply chain continuity and design flexibility.
Technical Context
The MAX6890ETI+ implements a digital logic network that routes inputs (six voltage detectors IN1–IN6, four GPIs, MR, MARGIN) through independently programmable timing blocks to drive eight conditional outputs (PO1–PO8). Each output's assertion/deassertion is governed by user-defined event triggers and delay settings stored in on-chip configuration EEPROM.
Its dual-power architecture uses either IN1 (≥6.5V) or the highest of IN2–IN6 (≥2.7V) to generate internal VCC (5.4V LDO) and DBP (2.55V LDO); all voltage detectors feature high-Z mode enabling sub-1V threshold detection via external dividers, and the watchdog timer supports independent initial/normal timeout programming from 6.25ms to 102.4s.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Count | Six configurable voltage detector inputs (IN1–IN6): IN1/IN6 support 1.25V–15.25V range; IN2–IN6 support 0.5V–5.5V in 10mV/20mV steps. |
| Programmable Outputs | Eight outputs (PO1–PO8), each configurable as active-high, active-low, open-drain, or weak pullup with 6.6kΩ–15kΩ pullup resistance. |
| Timing Delay Range | 25µs to 1600ms per output - enables precise staggered rail enable/disable sequences across complex multi-voltage systems. |
| Threshold Accuracy | ±1% over temperature (−40°C to +85°C) for most thresholds - ensures reliable undervoltage detection without calibration. |
| Interface | SMBus/I²C-compatible 2-wire serial interface (400kHz max) with A0/A1 address pins - allows up to four devices on one bus for scalable supervision. |
| EEPROM | 512-bit user EEPROM (100,000 write cycles, 10-year retention) + configuration EEPROM - stores custom sequencing logic persistently across power cycles. |
| Supply Range | Powered from monitored rails: IN1 ≥4V or IN2–IN6 ≥2.7V; internal VCC = 5.4V (LDO-regulated from IN1), DBP = 2.55V. |
Pinout & Package
MAX6890ETI+ is housed in a 28-pin, 5mm × 5mm × 0.8mm thin QFN-EP package with exposed paddle (internally connected to GND). Pinout is validated per Maxim's official datasheet Rev 1 (19-3595).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PO1–PO8 | Programmable output terminals | Each drives system reset, enable, or interrupt signals; defaults to 10µA pulldown below UVLO (2.5V), then assumes programmed state (active-H/L, OD, weak PU) above UVLO. |
| IN1, IN6 | High-voltage detector inputs | IN1: 1.25V–13.2V (25/50mV steps); IN6: 0.5V–5.5V (10/20mV steps); both require 0.1µF local bypass for noise immunity. |
| IN2–IN5 | Standard voltage detector inputs | Each monitors 0.5V–5.5V rails with ±1% accuracy; high-Z mode enables 0.167V–1.017V detection using external resistor dividers. |
| MARGIN, MR | System control inputs | MARGIN overrides MR to hold outputs in current state; both are internally pulled up to DBP (2.55V) via 10µA current sources. |
| SDA, SCL, A0, A1 | I²C/SMBus interface | Open-drain SDA/SCL require external pullups; A0/A1 set device address (up to 4 MAX6890ETI+ on one bus). |
| GPI1–GPI4 | General-purpose logic inputs | Four inputs configurable as watchdog triggers or output condition enablers; each pulled to GND via 10µA sink. |
| VCC, DBP | Internal power rails | VCC (5.4V) powers analog circuitry; DBP (2.55V) powers EEPROM, logic, and outputs - both require 1µF ceramic bypass to GND. |
| GND, EP | Ground reference | Pin 4 and exposed paddle (EP) are internally tied to system ground - mandatory low-inductance connection for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable voltage detection | Six independent inputs with selectable ranges (e.g., IN1: 1.25V–13.2V in 25mV steps) and ±1% accuracy - eliminates need for external resistive dividers in most applications. |
| Eight flexible output types | Each PO supports active-high, active-low, open-drain, or weak pullup with programmable timing - enables direct interfacing with diverse reset controllers, FPGAs, and PMICs without level-shifting. |
| Watchdog timer with dual timeouts | Independent initial (6.25ms–102.4s) and normal timeout periods, triggerable by GPI or PO - provides fail-safe recovery for boot-up and runtime phases. |
| Persistent configuration storage | On-chip configuration EEPROM retains sequencing logic across power loss - removes dependency on host processor for reinitialization. |
| Multi-rail power sourcing | Auto-selects power from highest valid input (IN1 ≥4V or IN2–IN6 ≥2.7V) - simplifies board-level power architecture and improves system robustness. |
Applications
| Telecom Central Office Systems | Server Power Sequencing |
|---|---|
|
Use Scenario: Managing startup/shutdown sequencing of multiple voltage rails (12V, 5V, 3.3V, 1.8V, 1.2V) in carrier-grade line cards with strict timing windows. IC Role / Device Role / Timing Role: Primary sequencer supervising six rail voltages and driving eight enable/reset signals with sub-millisecond timing resolution. Use Value: Ensures ASICs and FPGAs receive power in correct order and remain held in reset until all supplies stabilize - prevents latch-up and configuration corruption. |
Use Scenario: Coordinating power-up of CPU, memory, and peripheral rails in dual-socket x86 servers where BIOS requires deterministic rail ramp timing. IC Role / Device Role / Timing Role: Configurable supervisor executing pre-programmed sequence stored in EEPROM, triggered by power-good signals and manual reset. Use Value: Eliminates need for discrete timers and logic gates; reduces BOM count and PCB area while supporting field-updatable sequencing logic. |
| Wireless Base Stations | Storage Equipment |
|
Use Scenario: Monitoring and sequencing RF front-end, digital baseband, and auxiliary supplies in 4G/5G macrocell units operating in extended temperature range. IC Role / Device Role / Timing Role: Six-input voltage supervisor with watchdog-triggered fail-safe reset, operating reliably from −40°C to +85°C. Use Value: Maintains system integrity during thermal cycling and brownout events; margin disable input supports factory calibration without hardware modification. |
Use Scenario: Controlling power sequencing for SAS/SATA SSD backplanes with mixed 12V, 5V, and 3.3V rails and hot-swap capability. IC Role / Device Role / Timing Role: Eight-output sequencer managing rail enables, reset asserts, and fault signaling to RAID controller and drive firmware. Use Value: Enables graceful power-down on overtemperature or overcurrent events via GPI-triggered output reconfiguration - improves data integrity and MTBF. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power-supply sequencing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6889ETJ+ | Eight voltage inputs (IN1–IN8), ten programmable outputs, adds IN7/IN8 high-voltage monitoring - larger pin count (32-pin QFN) and higher channel density. | Required when supervising >6 rails or needing dual high-voltage inputs (e.g., 12V + 48V monitoring); not drop-in compatible due to pinout and footprint differences. | Select MAX6889ETJ+ only if additional inputs/outputs are needed; MAX6890ETI+ remains optimal for six-rail systems with space-constrained layouts. |
| TPS659122ZQW | TI PMIC with integrated DC/DC converters and LDOs; includes sequencer but lacks EEPROM configurability and independent timing per output. | Used in SoC-centric designs where power conversion + sequencing are co-integrated; requires host processor initialization and offers no persistent configuration. | Choose TPS659122ZQW for cost-sensitive, single-SoC platforms; MAX6890ETI+ is preferred for field-updatable, processor-agnostic, multi-board sequencing. |
Compared with MAX6889ETJ+, MAX6890ETI+ reduces pin count and layout complexity for six-rail systems; versus TPS659122ZQW, it delivers standalone, EEPROM-based sequencing without host dependency or integrated regulation - critical for modular, multi-vendor power architectures.
Availability
MAX6890ETI+ is available at Aetrix Electronics and suitable for telecom central office systems, server power sequencing, and wireless base station designs requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for MAX6890ETI+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for demanding industrial, communications, and computing applications - known for high-reliability power management and interface solutions.
The MAX6889/MAX6890/MAX6891 product line was engineered specifically for EEPROM-configurable, multi-rail power sequencing in high-availability systems where deterministic startup, field-updatable logic, and wide input voltage monitoring are essential.
FAQ
What is the exact number and type of voltage detector inputs supported by the MAX6890ETI+?
The MAX6890ETI+ features six voltage detector inputs: IN1 (high-voltage, 1.25V–13.2V), IN2–IN5 (standard, 0.5V–5.5V), and IN6 (standard, 0.5V–5.5V). All support programmable thresholds in 10mV or 20mV increments, and IN1/IN6 also support 25mV/50mV steps. This configuration is fixed per the MAX6890 family and differs from the eight-input MAX6889ETJ+ and four-input MAX6891ETP+.
Does the MAX6890ETI+ require an external microcontroller to configure its sequencing behavior?
No - the MAX6890ETI+ stores all sequencing logic, timing delays, and output configurations in on-chip EEPROM. Once programmed via the I²C/SMBus interface, it operates autonomously at power-up without host intervention. The MAX6890ETI+ retains its configuration across power cycles, enabling true "set-and-forget" power management in headless systems.
Can the MAX6890ETI+ monitor sub-1V supply rails such as 0.85V or 0.65V?
Yes - by configuring any IN2–IN6 input to high-impedance (high-Z) mode and adding an external resistor divider, the MAX6890ETI+ achieves 0.167V–1.017V detection in 3.3mV steps. This capability is explicitly documented in the MAX6890ETI+ datasheet and does not require additional ICs or calibration.
What is the maximum timing delay achievable per programmable output on the MAX6890ETI+?
The MAX6890ETI+ supports a maximum programmable timing delay of 1600ms per output (PO1–PO8), adjustable in discrete steps from 25µs up to that limit. This value is confirmed in the Electrical Characteristics table (tRP parameter, code "111") and applies identically across all eight outputs under standard operating conditions (−40°C to +85°C).
How does the MAX6890ETI+ handle power supply during system startup when multiple input rails are present?
The MAX6890ETI+ uses a virtual diode-ORing scheme to auto-select power from the highest valid input: IN1 ≥4V or IN2–IN6 ≥2.7V. If IN1 > 6.5V, it powers the internal 5.4V LDO (VCC); otherwise, the highest IN2–IN6 rail supplies VCC. Internal hysteresis prevents rail-switching oscillation when inputs are within 50mV - a behavior verified in the "Powering the MAX6889/MAX6890/MAX6891" section.
MAX6890ETI+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 6
- Voltage - Threshold:
- 6 Selectable Threshold Combinations
- Output:
- Open Drain, Open Drain
- Reset:
- Active High/Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TQFN (5x5)
MAX6890ETI+ FAQ
1.How can I place an order for MAX6890ETI+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX6890ETI+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX6890ETI+ reliable?
The price and inventory of MAX6890ETI+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX6890ETI+ is usually 5 days.
3.What payment methods are accepted for MAX6890ETI+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX6890ETI+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX6890ETI+?
MAX6890ETI+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX6890ETI+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX6890ETI+?
For technical support, including MAX6890ETI+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX6890ETI+ requirements.
6.How does Aetrix verify that MAX6890ETI+ is sourced from the original manufacturer or authorized distributors?
All MAX6890ETI+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX6890ETI+ meets industry standards.
7.What is the process for return or replacement of MAX6890ETI+?
All MAX6890ETI+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX6890ETI+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX6890ETI+ part is unused and in its original packaging.
Return procedure for MAX6890ETI+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX6890ETI+ Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

