Analog Devices Inc./Maxim Integrated MAX693ACPE

Overview

The MAX693ACPE from Maxim Integrated is a microprocessor supervisory circuit designed for 5V systems requiring reliable power-up reset, watchdog monitoring, and battery-backed RAM protection. It features a 4.4V typical reset threshold, 200ms reset timeout, 30μA operating supply current, and integrated chip-enable gating with ≤10ns propagation delay. It is used in industrial controllers and intelligent instruments where brownout immunity and data integrity during power failure are critical.

For engineers reviewing the MAX693ACPE datasheet, MAX693ACPE pinout, MAX693ACPE application, or MAX693ACPE equivalent, key selection criteria include its guaranteed RESET assertion down to VCC = 1V, ±2% power-fail accuracy (shared with MAX800M), battery switchover hysteresis of 60mV, and compatibility with MaxCap®/SuperCap™ backup capacitors.

Technical Context

The MAX693ACPE implements dual reset outputs (active-low RESET and active-high RESET), a three-level watchdog input (WDI) with selectable timeout periods (100ms short / 1.6s long), and an uncommitted power-fail comparator (PFI/PFO) with 1.25V threshold and 25μs response. Its internal oscillator or external capacitor/clock at OSC IN sets timing, while OSC SEL selects between internal and external timebases.

It integrates bidirectional VCC/VBATT switchover with 0.8Ω VCC-to-VOUT on-resistance and 15–30Ω VBATT-to-VOUT on-resistance, enabling seamless transition to backup power when VCC drops below VBATT − 0.3V. The CE IN/CE OUT transmission gate provides 75Ω series impedance and supports high-speed μP bus interfacing without data corruption during reset assertion.

Key Specifications

Pinout & Package

MAX693ACPE is supplied in a 16-pin plastic DIP (dual in-line package) with 0.3-inch body width and through-hole mounting. Pin spacing is 0.1 inch, compatible with standard PCB layouts and socketing for prototyping and repair.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX693ACPE, MAX800MCPE offers broader temperature support without sacrificing accuracy or functionality, while MAX691ACPE trades PFI precision and lower reset voltage for legacy compatibility - neither is pin-compatible without verifying board-level timing and threshold requirements.

Availability

MAX693ACPE is available at Aetrix Electronics and suitable for industrial controllers, intelligent instruments, and critical μP power monitoring applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for MAX693ACPE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, medical, and communications applications, emphasizing reliability, low power, and integration.

The MAX691A/MAX693A family was engineered specifically for robust microprocessor supervision in noise-prone, wide-temperature environments - delivering guaranteed reset behavior, battery switchover, and hardware-enforced memory protection.

FAQ

What is the guaranteed minimum VCC level at which MAX693ACPE asserts RESET?

The MAX693ACPE guarantees RESET assertion remains valid down to VCC = 1V. This is achieved via internal circuitry that maintains gate drive to the open-drain RESET output even as VCC collapses. At VCC = 1V and sinking 50μA, RESET voltage is specified at 0.004V to 0.3V - ensuring reliable μP reset initiation well below standard 5V brownout thresholds. This behavior is confirmed in the Electrical Characteristics table under "RESET Output Voltage".

Does MAX693ACPE support external timing for watchdog and reset functions?

Yes, MAX693ACPE supports external timing via OSC IN and OSC SEL pins. When OSC SEL is driven low, OSC IN accepts either an external clock signal or a timing capacitor to ground. With a 47pF capacitor, the reset timeout is 2048 clock cycles and long watchdog timeout is 4096 cycles - both fixed values independent of process or temperature per datasheet Note 4. This allows precise, repeatable timing not subject to internal oscillator drift.

How does the CE IN/CE OUT gating function protect CMOS RAM during power failure?

The MAX693ACPE disables the CE IN-to-CE OUT path automatically when RESET is asserted - i.e., during power-up, brownout, or watchdog timeout. In this state, CE OUT is actively pulled to VOUT, preventing spurious chip-select pulses from reaching RAM. The transmission gate has ≤10ns propagation delay and 75Ω series impedance, ensuring no timing violation on fast buses. This hardware-enforced gating eliminates reliance on software write-protection routines during unstable power conditions.

What is the role of the BATT ON pin on MAX693ACPE, and what load can it drive?

The BATT ON pin on MAX693ACPE is an open-drain output that goes high when VOUT switches from VCC to VBATT - signaling active battery backup. It sinks 3.2mA at 0.1V saturation when low (VCC active), and sources ~10μA when high (battery active). It can directly drive LEDs or provide base current to a PNP transistor for higher-current backup switching, as shown in the Typical Operating Circuit. Its logic state is strictly tied to the internal switchover comparator, not reset status.

Can MAX693ACPE monitor both main supply and battery voltage independently?

MAX693ACPE monitors VCC continuously for reset generation and switchover control, and uses PFI (power-fail input) as an independent, uncommitted comparator input with 1.25V threshold - allowing separate monitoring of battery voltage or auxiliary rails. While VBATT is used only for switchover and backup supply, PFI can be connected to a resistor divider from any voltage source. Its ±25nA leakage and 25μs response ensure accurate, low-interference monitoring without loading the sensed node.