Analog Devices Inc./Maxim Integrated MAX695EWE-T

Overview

The MAX695EWE-T from Maxim Integrated is a 16-pin microprocessor supervisory circuit providing precision reset generation, adjustable watchdog timer, battery backup switchover, power-fail detection, and CE gating for CMOS RAM write protection. It features a 4.65V reset threshold, 200ms reset timeout, 1.6s/100ms selectable watchdog period, 1.3V PFI comparator, and operates from -40°C to +85°C in SOIC-Wide package.

For engineers reviewing the MAX695EWE-T datasheet, MAX695EWE-T pinout, MAX695EWE-T application, or MAX695EWE-T equivalent, key selection criteria include its adjustable reset/watchdog timing, integrated CE output for RAM write protection, VCC/VBATT switchover with 70mV rise/50mV fall hysteresis, and compatibility with 5V ±5% supplies.

Technical Context

The MAX695EWE-T implements a dual-threshold voltage monitor (4.65V reset, 1.3V PFI), an internal oscillator with OSC SEL/OSC IN configurable timing, and a battery switchover circuit using a 200Ω MOSFET for low-dropout VBATT-to-VOUT connection. Its CE gating logic forces CE OUT high when VCC falls below 4.65V, independent of CE IN state.

It integrates a three-level WDI input that disables the watchdog when floating or mid-supply, and provides separate active-low RESET and active-high RESET outputs, plus WDO and LOW LINE signals for system status monitoring and fault isolation.

Key Specifications

Pinout & Package

MAX695EWE-T is housed in a 16-pin SOIC-Wide (0.300" wide) package with 1.27mm pitch, RoHS-compliant, moisture-sensitive level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX695CWE+ and MAX695MJE, the MAX695EWE-T delivers identical supervisory functionality and timing flexibility at industrial temperature range (-40°C to +85°C), making it the optimal balance of performance, qualification, and cost for most embedded OEM designs.

Availability

MAX695EWE-T is available at Aetrix Electronics and suitable for industrial control systems, automotive telematics units, medical diagnostic equipment, and smart energy meters requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MAX695EWE-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, automotive, communications, and computing markets.

The MAX690–MAX695 family was engineered specifically for robust µP supervision in mission-critical embedded systems-integrating reset, watchdog, battery switchover, and memory protection in a single 16-pin IC.

FAQ

What is the reset timeout delay of the MAX695EWE-T, and how is it configured?

The MAX695EWE-T has a nominal reset timeout delay of 200ms after VCC rises above 4.65V. This value is fixed for the MAX695EWE-T variant and cannot be adjusted externally-it differs from the MAX690/MAX692 which use 50ms. The 200ms delay ensures sufficient time for crystal oscillator startup and µP initialization before release from reset. This timing is factory-trimmed and specified over the full -40°C to +85°C operating range. The MAX695EWE-T achieves this via internal monostable circuitry tied to the OSC SEL/OSC IN configuration, but unlike other members of the family, its reset delay is not user-selectable.

Does the MAX695EWE-T support battery backup switchover, and what are the voltage limits?

Yes, the MAX695EWE-T supports automatic battery backup switchover between VCC and VBATT. It connects VOUT to the higher of the two supplies using an internal 200Ω MOSFET for VBATT path and a PNP transistor for VCC path. VBATT operates from 2.0V to 4.25V, and VCC from 4.75V to 5.5V. Switchover occurs with 70mV hysteresis on power-up and 50mV on power-down to prevent oscillation. During backup mode (VCC < VBATT − 0.2V), VOUT delivers VBATT − 0.1V at 250µA, and quiescent current is ≤1µA-enabling multi-year operation on CR2032 cells. The BATT ON output actively drives external PNP transistors to extend VOUT current beyond 50mA.

How does the CE gating function work on the MAX695EWE-T, and why is it important?

The MAX695EWE-T's CE gating uses CE IN and CE OUT pins to prevent invalid writes to battery-backed CMOS RAM during power transients. When VCC ≥ 4.65V, CE OUT replicates CE IN with ~50ns delay. If VCC drops below 4.65V, CE OUT is forced high regardless of CE IN state-effectively disabling RAM writes. This hardware-enforced write protection eliminates software race conditions and ensures data integrity during power-up, brownout, or reset events. It is critical in systems where µP may execute spurious code or glitchy I/O during unstable supply conditions. The MAX695EWE-T is one of only two variants in the MAX690 family (with MAX691/MAX693) offering this feature.

Can the watchdog timer on the MAX695EWE-T be disabled, and how?

Yes, the watchdog timer on the MAX695EWE-T can be fully disabled by leaving the WDI pin unconnected (floating). The device internally biases WDI to ~38% of VCC via a 125kΩ impedance, placing it in a mid-supply "inactive" state that prevents timer activation. No external pull-up or pull-down is required. Alternatively, driving WDI continuously high or low will cause repeated 200ms RESET pulses every 1.6s (long timeout) or 100ms (short timeout, if OSC SEL/OSC IN configured accordingly). Disabling the watchdog is confirmed in the datasheet's Note 2 and Figure 7 block diagram, where floating WDI places the watchdog fault flip-flop in reset state.

What is the purpose of the PFI and PFO pins on the MAX695EWE-T, and how are they used in practice?

The PFI (Power-Fail Input) and PFO (Power-Fail Output) pins on the MAX695EWE-T implement a dedicated 1.3V comparator for early power-fail detection. PFI accepts a scaled-down version of the system's main supply (e.g., via resistor divider from +5V or unregulated input), and asserts PFO low when PFI < 1.3V. This provides 1–2ms advance warning before VCC crosses the 4.65V reset threshold-enough time for the µP to save critical data to RAM or EEPROM. PFO is open-drain and can directly drive NMI inputs or external alarms. Importantly, the PFI comparator is automatically disabled when VCC < VBATT, conserving battery current during backup operation-a key design feature confirmed in the "Detailed Description" section of the datasheet.