Analog Devices Inc./Maxim Integrated MAX697CWE+

Overview

MAX697CWE+ from Maxim Integrated is a microprocessor supervisory circuit designed for power-supply monitoring and CMOS RAM write protection in embedded systems. It provides adjustable low-line reset (1.25V–1.35V), watchdog timeout (100ms or 1.6s), power-fail warning (1.3V PFI threshold), 50ms reset pulse width, and chip-enable gating - all in a 16-pin wide SO package rated for 0°C to +70°C operation.

For engineers reviewing the MAX697CWE+ datasheet, MAX697CWE+ pinout, MAX697CWE+ application, or MAX697CWE+ equivalent, key selection criteria include its 160–300µA supply current, CE IN/CE OUT write-protection logic, absence of battery-switching circuitry (vs. MAX696), 1.3V precision reference, and dual watchdog timing modes enabled via OSC SEL and OSC IN.

Technical Context

The MAX697CWE+ integrates six core supervisory functions: precision 1.3V low-line detection with hysteresis, programmable watchdog timer with internal oscillator or external clock/capacitor timing, dedicated power-fail comparator (PFI/PFO), active-high and active-low RESET outputs, and CMOS RAM write-protection via CE IN → CE OUT gating. Its architecture separates critical monitoring paths - LLIN feeds both reset generation and LOW LINE output, while PFI operates independently for early power-fail warning.

Unlike the MAX696, the MAX697CWE+ omits VBATT, VOUT, and BATT ON pins, eliminating battery-backup switching but enabling lower quiescent current (<300µA) and adding CE IN/CE OUT functionality. The watchdog timer features two-stage timeout behavior: extended period (1.6s) immediately after reset, then standard period (100ms or 1.6s) upon first WDI transition - preventing false triggers during initialization.

Key Specifications

Pinout & Package

MAX697CWE+ is housed in a 16-pin Wide SO (SOIC-W) package with 300 mil body width and standard 1.27mm pitch. Pin 12 is NC; pins 1 and 2 are unused (no VBATT/VOUT); CE IN (pin 13) and CE OUT (pin 12 is NC, so CE IN/CE OUT are pins 13 and - per datasheet pin table - pin 12 is NC for MAX697, and CE OUT is pin 12? Wait - correction: per "Pin Description (continued)" section, CE OUT is pin 12 and CE IN is pin 13 for MAX697. Confirmed: MAX697 pin 12 = CE OUT, pin 13 = CE IN. Pin 1 = TEST (ground), pin 2 = NC (not connected). All other pins match MAX696 functional mapping except missing VBATT/VOUT/BATT ON.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX696CWE+, the MAX697CWE+ trades battery-switching capability for lower power and integrated CE gating - making it optimal for write-critical, low-quiescent applications. Compared with TPS3808G33DBVR, it delivers full supervisory functionality at the cost of larger footprint and higher BOM count, but enables robust system-level reliability.

Availability

MAX697CWE+ is available at Aetrix Electronics and suitable for industrial controllers, medical instrumentation, smart energy meters, and automated test equipment requiring stable component supply across extended temperature and lifecycle demands.

Supply support for MAX697CWE+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated, now part of Analog Devices, designs precision analog and mixed-signal ICs for industrial, communications, and computing applications - emphasizing reliability, integration, and low-power operation.

The MAX697CWE+ belongs to Maxim's microprocessor supervisory product line, engineered specifically for embedded systems requiring coordinated power monitoring, fault detection, and nonvolatile memory protection without battery management overhead.

FAQ

What is the function of the CE IN and CE OUT pins on the MAX697CWE+?

The CE IN pin (pin 13) accepts the system's chip-enable or write signal, which is buffered and gated by the MAX697CWE+ to produce CE OUT (pin 12). When LLIN voltage drops below 1.3V, CE OUT is forced high - disabling writes to connected CMOS RAM or EEPROM regardless of CE IN state. This ensures data integrity during power faults. The MAX697CWE+ implements this with 50ns propagation delay and rail-to-rail CMOS output drive.

Does the MAX697CWE+ support battery backup switching like the MAX696?

No, the MAX697CWE+ does not support battery backup switching. It lacks VBATT, VOUT, and BATT ON pins entirely - a deliberate design choice to reduce quiescent current (to 160–300µA) and add CE IN/CE OUT write-protection functionality. Battery switchover is exclusive to the MAX696 family. If backup power management is required, the MAX696CWE+ is the appropriate alternative, but it cannot perform CE gating.

How is the watchdog timeout period configured on the MAX697CWE+?

The MAX697CWE+ watchdog timeout is selected via OSC SEL (pin 7) and OSC IN (pin 6). With OSC SEL high or floating, OSC IN sets short (100ms) or long (1.6s) timeout using internal oscillator. With OSC SEL low, OSC IN accepts external clock or capacitor for custom timing (e.g., 400ms/47pF × C). Critically, the first timeout after reset is always 1.6s - preventing false triggers during firmware initialization - then switches to the selected mode on first WDI transition.

What is the purpose of the PFI and PFO pins on the MAX697CWE+?

PFI (pin 8) is the noninverting input to a dedicated 1.3V comparator; connecting it to a resistor divider on an unregulated supply enables early power-fail detection before the main VCC rail collapses. PFO (pin 9) is the open-drain output that goes low when PFI < 1.3V - typically used to assert a nonmaskable interrupt (NMI) to the microprocessor, triggering immediate data save routines. Unlike the main reset path, PFO operates independently and activates earlier - providing critical warning margin.

Can the reset timeout delay of the MAX697CWE+ be adjusted, and how?

Yes, the MAX697CWE+ reset timeout delay can be adjusted from the default 50ms. With OSC SEL high/floating, the delay is fixed at 50ms. To vary it, tie OSC SEL low and connect an external capacitor between OSC IN (pin 6) and GND - delay scales inversely with capacitance (e.g., 47pF yields ~200ms, 100pF yields ~100ms). Alternatively, drive OSC IN with an external clock signal for precise, programmable timing. All adjustments maintain the same 1.3V threshold and hysteresis behavior.