Analog Devices Inc./Maxim Integrated MAX72420+

Overview

MAX72420+ from Maxim Integrated is a highly integrated baseboard and storage management controller featuring a 32-bit RISC engine, 10/100 Ethernet MAC with RMII/NC-SI support, four I²C interfaces (including IPMB-capable), two UARTs with hardware flow control, 54 GPIOs, 64KB zero-wait-state SRAM, and an EJTAG debug port - deployed in server management and storage enclosure control systems.

For engineers reviewing the MAX72420+ datasheet, MAX72420+ pinout, MAX72420+ application, or MAX72420+ equivalent, key selection considerations include its LPC interface option, dual/quad SPI flash support, NC-SI/RMII network controller interfacing, fan-speed monitoring capability (32 inputs), and PWM output provision (32 channels) for thermal and power management subsystems.

Technical Context

The MAX72420+ integrates a proprietary MX3 32-bit RISC core with on-chip 64KB SRAM for deterministic firmware execution and supports configurable low-pin-count (LPC) bridging to host platforms. Its Ethernet MAC operates exclusively via RMII or NC-SI - not as a standalone PHY - requiring external network controller coordination.

It implements four multimaster-capable I²C interfaces compliant with IPMB-1.0 for SES/SAF-TE communication, plus a high-speed I²C core for fast peripheral access. The device supports optional SWS interface for LM32/LM41/LM95010 sensors and provides 32 PWM outputs with programmable duty cycle and frequency.

Key Specifications

Pinout & Package

The MAX72420+ is housed in an 88-ball chip-scale ball-grid array (CSBGA) package with 0.5mm pitch and 8.2mm × 8.2mm footprint. Ball mapping includes dedicated RMII/NC-SI signal groups, four I²C bus banks, dual UART TX/RX/CTS/RTS sets, 32 PWM output balls, 32 tachometer input balls, and configurable LPC interface pins (LAD[3:0], LFRAME#, LCLK, etc.).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar baseboard management controller applications.

Compared with ASPEED AST2500A1-BQFP and Microchip LAN9252, the MAX72420+ uniquely combines IPMB I²C, NC-SI/RMII, 32 PWM/tach pairs, and EJTAG in a single CSBGA package - enabling compact, thermally optimized BMC designs without external fan controllers or PHYs.

Availability

MAX72420+ is available at Aetrix Electronics and suitable for server baseboard management, storage enclosure control, and embedded thermal management applications requiring stable component supply despite NRND status.

Supply support for MAX72420+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and digital ICs for industrial, communications, computing, and consumer applications.

The MAX72420+ belongs to Maxim's embedded management controller product line, engineered specifically to consolidate baseboard, storage, and thermal management functions into a single cost-optimized SoC for space-constrained server and storage platforms.

FAQ

Is the MAX72420+ still in production, and what does NRND mean for design-in?

The MAX72420+ is Not Recommended for New Designs (NRND) and has reached end-of-life status per Maxim's product change notification. While limited inventory may be available through authorized channels, new designs should select alternatives with active support. Legacy designs using MAX72420+ remain supported with full documentation and known-good-binning data. Aetrix Electronics maintains traceable stock for continuity programs.

Does the MAX72420+ include an integrated Ethernet PHY, or is an external PHY required?

The MAX72420+ contains only a 10/100 Ethernet MAC - no integrated PHY. It connects to external PHYs or NC-SI-capable network controllers via RMII or NC-SI interface. This architecture reduces die size and power while enabling flexible PHY selection (e.g., Broadcom BCM54213, Microchip LAN8742A). The MAX72420+ datasheet specifies timing and signal integrity requirements for both RMII and NC-SI modes.

What is the function of the LPC interface on the MAX72420+, and how is it configured?

The LPC interface on the MAX72420+ provides optional direct bridging to host platform southbridge or PCH, enabling low-latency communication for BIOS/firmware handshaking and secure boot coordination. It is enabled via strap pins and configured in firmware using LPC configuration registers. Signals include LAD[3:0], LFRAME#, LCLK, and LRESET#. The MAX72420+ supports LPC 1.1 protocol timing and can operate at up to 33MHz.

Can the MAX72420+ support dual or quad SPI flash, and what performance benefit does this provide?

Yes, the MAX72420+ supports dual and quad SPI flash interfaces via dedicated IO pins and internal controller logic. Quad SPI mode doubles effective clock rate and quadruples data throughput versus standard SPI, reducing firmware read latency by up to 75%. This accelerates secure boot verification, firmware updates, and runtime code fetch - especially beneficial in systems with large IPMI firmware images.

How many independent I²C buses does the MAX72420+ support, and are they all IPMB-compliant?

The MAX72420+ supports four independent I²C interfaces, all fully compliant with IPMB-1.0 specification. Each interface includes dedicated SDA/SCL pins, programmable clock stretching, and hardware arbitration logic. These are used for SES/SAF-TE communication with storage backplanes, PSU telemetry, temperature sensors, and other IPMI-managed peripherals - enabling concurrent, non-blocking management traffic across multiple subsystems.