Analog Devices Inc./Maxim Integrated MAX761CSA+

Overview

MAX761CSA+ from Maxim Integrated is a high-efficiency, current-limited pulse-frequency-modulated (PFM) step-up DC-DC converter with internal 1A N-channel power MOSFET, fixed 12V output (±4% over temperature), 110µA max supply current, and 2V to 16.5V input range - designed for flash memory programming in battery-powered systems.

For engineers reviewing the MAX761CSA+ datasheet, MAX761CSA+ pinout, MAX761CSA+ application, or MAX761CSA+ equivalent, this page delivers verified technical context, real-world operating parameters, validated pin functions, confirmed alternatives, and supply-chain support for industrial and embedded power design.

Technical Context

The MAX761CSA+ uses a proprietary current-limited PFM control scheme that combines ultra-low quiescent current (≤110µA) with cycle-by-cycle peak-current limiting (1A) and fixed on-time (8µs)/off-time (1.3µs) one-shots to maintain regulation across load currents from 0mA to 150mA. It operates in continuous-conduction mode (CCM) under heavy loads and supports both bootstrapped (output-sensed) and non-bootstrapped (input-sensed) configurations.

Its integrated 1.5V reference (±30mV accuracy, 100µA sink/source capability) feeds the FB comparator and LBI low-battery detector, which features 20mV hysteresis and open-drain LBO output. The device includes undervoltage lockout (2.0V start-up in bootstrapped mode) and TTL/CMOS-compatible SHDN with <5µA shutdown current.

Key Specifications

Pinout & Package

MAX761CSA+ is housed in an 8-pin SO (Small Outline) package, 150mil width, RoHS-compliant, with standard JEDEC MS-012AC footprint and thermal pad not connected internally.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar step-up DC-DC converter applications.

Compared with MAX761CSA+, MAX770CPA+ offers higher output flexibility at the cost of increased component count and loss of integrated battery monitoring, while TPS61040DRVR provides lower quiescent current but omits the 12V fixed output, reference, and LBO functionality critical for flash programming systems.

Availability

MAX761CSA+ is available at Aetrix Electronics and suitable for flash memory programming, PCMCIA card power, and battery-powered instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for MAX761CSA+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, automotive, and communications markets.

The MAX761CSA+ belongs to Maxim's legacy high-efficiency, low-IQ DC-DC converter family, engineered specifically for battery-critical applications like flash memory programming where minimal quiescent current and robust start-up behavior are essential.

FAQ

What is the minimum input voltage required for MAX761CSA+ to start up?

The MAX761CSA+ guarantees start-up at 2.0V in bootstrapped mode (with internal feedback resistors). In non-bootstrapped mode using external resistors, undervoltage lockout raises the minimum start-up voltage to ~2.7V. This behavior is confirmed in the Electrical Characteristics table and Typical Operating Characteristics (Figure MAX761-07), where no-load start-up voltage remains ≤2.0V across -40°C to +85°C for bootstrapped operation. The MAX761CSA+ achieves this via dedicated start-up circuitry that fixes duty cycle at 50% until V+ reaches 2.5V.

Does MAX761CSA+ support adjustable output voltages, and how is it configured?

Yes, MAX761CSA+ supports adjustable output from 5V to 16.5V using external resistors R1 and R2 connected between V+, FB, and GND per Figure 3 and Figure 5. For bootstrapped adjustable operation, tie FB to the resistor divider midpoint instead of GND. The formula is R2 = R1 × (VOUT − 1.5V) / 1.5V, with R1 selected between 10kΩ and 250kΩ. Fixed 12V output is achieved by connecting FB directly to GND - a configuration validated in the Typical Operating Circuit (Figure 2) and Ordering Information section.

What is the role of the LBI and LBO pins on MAX761CSA+, and how are they used?

LBI is the low-battery comparator input, referenced to the internal 1.5V reference; LBO is its open-drain output. When LBI voltage falls below 1.5V, LBO pulls low (with 20mV hysteresis). To set a custom trip point (e.g., 3.3V), use R3 and R4 per R4 = R3 × (VTRIP − 1.5V) / 1.5V, with R3 ≤500kΩ. LBO must be pulled up externally (e.g., 100kΩ to VOUT). These functions are fully documented in the Pin Description and Applications Information sections, including hysteresis calculation and leakage current limits.

Can MAX761CSA+ operate in shutdown mode, and what happens to the output voltage?

Yes, MAX761CSA+ enters shutdown when SHDN is driven high (≥1.6V). In this state, internal bias and reference are disabled, supply current drops to <5µA, and VOUT collapses to V+ minus a diode drop (~0.4V) due to the parasitic path from V+ through the internal FET body diode to LX and output capacitor. LBO becomes high-impedance. This behavior is specified in the Electrical Characteristics table (Shutdown Current) and Detailed Description section, and is observable in the SHDN Response Time waveform (Figure).

What external components are required for basic MAX761CSA+ operation in bootstrapped 12V mode?

For fixed 12V bootstrapped operation, MAX761CSA+ requires: an 18µH surface-mount inductor (e.g., Sumida CD54-180), a Schottky catch diode (1N5817), 33µF output capacitor (low-ESR OS-CON or tantalum), 33µF input capacitor, 0.1µF REF bypass, and 0.1µF V+/GND ceramic decoupling. FB is tied to GND. This configuration is shown in Figure 2 and validated in the Typical Operating Circuit, with component values confirmed in the Design Procedure section and Table 1.