Analog Devices Inc./Maxim Integrated MAX792TESE

Overview

MAX792TESE from Maxim Integrated is a microprocessor supervisory circuit providing reset generation, manual reset input, two-stage power-fail warning (low-line detection 120mV above reset threshold), watchdog timer with pulsed fault output (WDPO), and chip-enable gating for CMOS RAM protection. It guarantees RESET validity down to VCC = 1V and supports internal or externally programmable reset/low-line thresholds. Used in embedded controllers requiring reliable brownout and software fault recovery.

For engineers reviewing the MAX792TESE datasheet, MAX792TESE pinout, MAX792TESE application, or MAX792TESE equivalent, key selection considerations include its 200ms reset timeout, ±2% threshold accuracy (in external programming mode), 10ns CE propagation delay, and dual active-high/active-low reset outputs - all critical for deterministic µP startup and memory write-cycle completion under undervoltage conditions.

Technical Context

The MAX792TESE integrates independent comparators for reset (with 1.30V internal reference), low-line (120mV above reset threshold), and overvoltage (1.30V threshold on OVI), plus a watchdog timer controlled by SWT capacitor value. Its chip-enable transmission gate disables during reset assertion, ensuring CE OUT remains low for 15µs after reset if CE IN is low - enabling safe RAM write-cycle completion.

It operates in two configuration modes: internal threshold mode (RESET IN/INT ≤ 60mV) uses factory-trimmed 1.30V reference; external programming mode (RESET IN/INT ≥ 600mV) allows resistor-divider setting of both reset and low-line thresholds. Watchdog timeout defaults to 1.6s (SWT = VCC) and scales linearly with SWT-to-GND capacitance (k = 16.2 ms/nF at VCC = 5V).

Key Specifications

Pinout & Package

MAX792TESE is housed in a 16-pin narrow SO (Small Outline) package, 3.9mm width, RoHS-compliant lead-free option available (suffix +).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX692AESA+ and TPS3808G33DBVR, the MAX792TESE delivers integrated low-line warning, pulsed watchdog fault signaling, and chip-enable gating - making it uniquely suited for systems requiring deterministic pre-reset notification, memory write protection, and multi-level fault response without external logic.

Availability

MAX792TESE is available at Aetrix Electronics and suitable for industrial PLC controllers, medical diagnostic instruments, automotive body control modules, and telecom remote terminal units requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MAX792TESE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, communications, and computing applications.

The MAX792TESE belongs to Maxim's microprocessor supervisory product line, engineered specifically for robust power-monitoring and fault-recovery in mission-critical embedded systems operating across -40°C to +85°C.

FAQ

What is the reset threshold voltage for MAX792TESE?

The MAX792TESE has a nominal reset threshold voltage of 2.91V (T suffix), with ±2% accuracy achievable in external programming mode using a resistor divider. In internal threshold mode, the device uses a factory-trimmed 1.30V reference, and the actual reset threshold depends on the external resistor network scaling - for example, a 2.91V threshold corresponds to a 2.25:1 ratio between R1+R2 and R2 in the divider. This value is confirmed in the Electrical Characteristics table on page 2 of the MAX792/MAX820 datasheet.

How does the watchdog timeout period work on MAX792TESE?

The MAX792TESE watchdog timeout defaults to 1.6 seconds when SWT is tied to VCC. To adjust it, connect a capacitor from SWT to GND: timeout = k × C (in nF), where k = 16.2 ms/nF at VCC = 5V and k = 27 ms/nF at VCC = 3V. The MAX792TESE datasheet specifies this relationship in the "Watchdog Timeout Period" section (page 3), and confirms capacitor values above 4.7nF are supported. WDPO pulses first, followed 70ns later by WDO assertion.

Can MAX792TESE be used with a 3.3V microprocessor?

Yes, the MAX792TESE operates from 2.75V to 5.5V and supports 3.3V systems directly. Its 2.91V reset threshold (T suffix) is ideal for 3.3V rails, providing ~12% headroom before reset assertion. All outputs - including RESET, WDO, and WDPO - are fully compatible with 3.3V logic levels, and the 10ns CE propagation delay ensures timing compliance with fast 3.3V µPs. This is verified in the Absolute Maximum Ratings and Electrical Characteristics tables.

What is the purpose of the LLIN/REFOUT pin on MAX792TESE?

On the MAX792TESE, the LLIN/REFOUT pin serves dual roles: in internal threshold mode (RESET IN/INT ≤ 60mV), it outputs a buffered 1.30V reference; in external programming mode (RESET IN/INT ≥ 600mV), it becomes the low-line comparator input. This pin enables flexible configuration - either using the internal reference for fixed thresholds or connecting an external resistor divider to set custom low-line and reset points. Its function is explicitly defined in the Pin Description table (page 7) and Detailed Description section.

Does MAX792TESE provide memory write-cycle completion support?

Yes, the MAX792TESE guarantees memory write-cycle completion via its CE gating architecture. When reset is asserted and CE IN is low, CE OUT remains low for 15µs after reset activation - ensuring ongoing RAM write operations complete before chip-enable is disabled. This behavior is documented in the "Chip-Enable Signal Gating" section (page 13) and confirmed in the CE IN to CE OUT timing specification (15µs hold time) in the Electrical Characteristics table.