Analog Devices Inc./Maxim Integrated MAX802SEPA+

Overview

MAX802SEPA+ from Maxim Integrated is a 3.3V/3.0V microprocessor supervisory circuit with active-low RESET output, precision 2.925V reset threshold (±2%), 200ms reset timeout, watchdog timer (1.6s), and battery-backup switchover. It monitors VCC supply integrity, asserts reset during brownout or watchdog timeout, and switches CMOS RAM to VBATT when VCC falls below 2.40V - used in embedded controllers and portable equipment requiring reliable power sequencing.

For engineers reviewing the MAX802SEPA+ datasheet, MAX802SEPA+ pinout, MAX802SEPA+ application, or MAX802SEPA+ equivalent, this page delivers verified electrical parameters, validated pin functions, confirmed battery-switching behavior, and real-world design implications for µP reset coordination, power-fail warning, and backup-power retention in battery-backed systems.

Technical Context

The MAX802SEPA+ integrates a precision reset comparator with 2.925V threshold (±2% tolerance on VCC falling), a 1.6s watchdog timer that clears on WDI edge transitions, and a dual-path power switch: VCC-to-VOUT via 3Ω PMOS and VBATT-to-VOUT via 140Ω NMOS. Switchover occurs at VSW = 2.40V (VBATT > VCC) and reverts only after VCC rises above VRST - not at VSW - ensuring stable recovery.

It features a dedicated PFI input (1.237V threshold, ±20mV hysteresis) for independent power-fail detection, open-drain PFO output, manual reset input (MR) with internal 70µA pull-up, and guaranteed RESET assertion down to VCC = 1.0V. All logic inputs tolerate voltages up to the higher of VCC or VBATT.

Key Specifications

Pinout & Package

MAX802SEPA+ is housed in an 8-pin plastic DIP (PDIP) package with 0.300" wide body, RoHS-compliant lead finish indicated by the '+' suffix.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microprocessor supervisory applications.

Compared with MAX802TEPA+, MAX802SEPA+ triggers reset earlier during VCC droop - critical for margin-constrained 3.0V designs - while MAX804SEPA+ provides interface flexibility at the cost of requiring an external pull-up resistor and careful noise immunity analysis.

Availability

MAX802SEPA+ is available at Aetrix Electronics and suitable for battery-powered computers and controllers, embedded controllers, and intelligent instruments requiring stable component supply with guaranteed long-term availability and traceable sourcing.

Supply support for MAX802SEPA+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for power management, sensing, and interface applications in industrial, medical, and communications systems.

The MAX802SEPA+ belongs to Maxim's µP supervisory family targeting 3.0V/3.3V systems, engineered to replace discrete reset networks with integrated reset generation, watchdog supervision, and seamless battery-backup switching.

FAQ

What is the exact reset threshold voltage of the MAX802SEPA+ and how tightly is it specified?

The MAX802SEPA+ has a nominal reset threshold of 2.925V, with ±2% tolerance on VCC falling (2.88V to 3.00V min/max). This tighter tolerance than legacy MAX690-series parts ensures predictable reset behavior in 3.3V ±10% and 3.0V ±10% systems. The specification is guaranteed over temperature and process variation, and appears in the Electrical Characteristics table under "Reset Threshold (VRST)" for MAX802S variants. The MAX802SEPA+ maintains this accuracy across its full operating range of -40°C to +85°C.

Does the MAX802SEPA+ support battery-backup operation when VBATT exceeds VCC?

Yes, the MAX802SEPA+ explicitly supports VBATT > VCC operation - a key design feature enabling use with standard 3.6V lithium cells. When VCC falls below the battery switchover threshold (VSW = 2.40V) and VBATT > VCC, the internal 140Ω NMOS switch connects VBATT to VOUT. The device remains functional with VBATT up to 6.0V, and the switchover logic prevents oscillation via 25mV hysteresis. This behavior is confirmed in the "Backup-Battery Switchover" section and Table 1 ("Input and Output Status in Battery-Backup Mode").

Can the watchdog timer in the MAX802SEPA+ be disabled?

No, the watchdog timer in the MAX802SEPA+ cannot be disabled. As stated in the "Watchdog Input" section: "Unlike the 5V MAX690 family, the watchdog function cannot be disabled." It continuously monitors WDI for edges; if no transition occurs within 1.6 seconds (1.12–2.24s over temperature), it triggers a reset pulse. The timer resets on any rising or falling edge at WDI, or while RESET is asserted. This hardwired behavior ensures fail-safe supervision even if firmware becomes unresponsive.

What is the function of the PFI and PFO pins on the MAX802SEPA+?

The PFI (Power-Fail Input) pin accepts an external voltage - typically derived from a resistor divider on an auxiliary supply - and compares it to a precise 1.237V internal reference. When PFI falls below this threshold, the PFO (Power-Fail Output) pin goes low. PFO is an open-drain output and can be used to generate a µP interrupt or drive the MR input of compatible devices like the MAX704/MAX806. This function operates completely independently of the main reset comparator and remains active only when VCC > VSW (≈2.40V), as detailed in the "Power-Fail Comparator" subsection.

Is the RESET output of the MAX802SEPA+ push-pull or open-drain?

The RESET output of the MAX802SEPA+ is a push-pull (active-drive) output, not open-drain. It actively drives low during reset assertion and high when deasserted - unlike the MAX804/MAX805 variants, which feature open-drain active-high RESET. This allows direct connection to µP reset inputs without external pull-up resistors. The datasheet confirms this in the Pin Description table (pin 7: "Active-Low Reset Output") and in Figure 2's timing diagram, where RESET transitions cleanly between rail-to-rail logic levels.