Analog Devices Inc./Maxim Integrated MAX8559ETAG2+T
- Part No.:
- MAX8559ETAG2+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
MAX8559ETAG2+T.pdf
- Description:
- IC REG LINEAR 3V/1.8V 8TDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MAX8559ETAG2+T from Maxim Integrated is a dual, low-noise, low-dropout linear regulator delivering 300mA per channel from 2.5V–6.5V input, with factory-preset outputs of 3.0V (OUTA) and 1.8V (OUTB), 60mV dropout at 100mA, 32µVRMS output noise, and independent logic-controlled shutdown inputs-designed for power rail sequencing in portable digital cameras and wireless LAN cards.
For engineers reviewing the MAX8559ETAG2+T datasheet, MAX8559ETAG2+T pinout, MAX8559ETAG2+T application, or MAX8559ETAG2+T equivalent, key selection criteria include dual-output voltage pairing, UCSP/TDFN package compatibility, thermal shutdown behavior at +160°C, PSRR of 70dB at 10kHz, and absence of required bypass capacitor for minimal footprint designs.
Technical Context
The MAX8559ETAG2+T integrates two independent P-channel MOSFET pass transistors (0.6Ω RDS(ON)) with internal 1.25V bandgap reference and error amplifiers, enabling load-dependent dropout and ultra-low quiescent current (115µA per LDO). Its autodischarge circuitry pulls each output to GND via 385Ω during shutdown.
It features separate SHDNA/SHDNB inputs that control individual LDOs or jointly disable both regulators and the internal reference-reducing supply current to 0.01µA. The BP pin accepts a 0.01µF ceramic capacitor to form an RC filter that suppresses reference noise, directly enabling the 32µVRMS output noise specification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage Pair | 3.0V (OUTA) / 1.8V (OUTB), factory-preset-enables simultaneous powering of core logic and I/O rails without external feedback resistors. |
| Max Output Current | 300mA per channel-supports high-current digital loads like image sensors or WLAN baseband ICs with 4.7µF output capacitors. |
| Dropout Voltage | 60mV at 100mA load-extends battery runtime by allowing regulation down to VIN = VOUT + 60mV, critical for Li-ion end-of-discharge operation. |
| Output Noise | 32µVRMS (100Hz–100kHz, with 0.01µF BP cap)-meets low-noise analog supply requirements for ADCs, RF front-ends, and precision references. |
| PSRR | 70dB at 10kHz-rejects switching noise from adjacent DC-DC converters, reducing need for additional filtering in mixed-signal systems. |
| Quiescent Current | 115µA per LDO (no load)-preserves battery life in always-on subsystems such as real-time clocks or sensor wake-up circuits. |
| Thermal Shutdown | +160°C activation with 10°C hysteresis-prevents permanent damage during sustained overload or poor PCB thermal design. |
Pinout & Package
MAX8559ETAG2+T is packaged in an 8-pin TDFN-EP (3mm × 3mm, exposed paddle), optimized for thermal dissipation in space-constrained portable applications. The exposed paddle must be soldered to the PCB ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (INA) | LDO A Input | Primary input for OUTA; shares common input node with INB-requires 2.2µF ceramic bypass to GND for stability up to 150mA loads. |
| 2 (SHDNA) | Shutdown A Control | Active-low logic input; pulling low disables OUTA and discharges it via internal 385Ω resistor-enables dynamic power gating of peripheral rails. |
| 3 (SHDNB) | Shutdown B Control | Active-low logic input; independent of SHDNA-allows asymmetric enable/disable sequencing between 3.0V and 1.8V domains. |
| 4 (INB) | LDO B Input | Primary input for OUTB; electrically tied to INA-supports single-input dual-output architecture with shared input filtering. |
| 5 (OUTB) | LDO B Output | Regulated 1.8V output sourcing up to 300mA; internally discharged to GND in shutdown-prevents backfeeding into powered-down circuitry. |
| 6 (GND) | Ground Reference | Common return path for both LDOs and internal circuitry-must be low-impedance connection to minimize noise coupling and voltage drop. |
| 7 (BP) | Reference Bypass | Connects to internal bandgap reference; 0.01µF ceramic cap here reduces output noise by filtering reference ripple-omitting it increases noise to 254µVRMS. |
| 8 (OUTA) | LDO A Output | Regulated 3.0V output sourcing up to 300mA; identical discharge behavior to OUTB-supports clean supply for microcontrollers or memory interfaces. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent shutdown controls | SHDNA and SHDNB allow granular power sequencing-e.g., hold 1.8V rail active while disabling 3.0V rail during sleep mode. |
| P-channel MOSFET pass transistors | 0.6Ω RDS(ON) enables low dropout proportional to load-unlike PNP-based regulators, no base-drive current waste improves light-load efficiency. |
| No mandatory bypass capacitor | Stable operation without BP capacitor reduces BOM count and board area-trade-off is higher output noise (254µVRMS vs. 32µVRMS). |
| Internal current limiting | 310mA minimum current limit per channel-protects against short-circuits without external components while maintaining continuous operation under fault. |
| Thermal overload protection | Independent thermal detectors per LDO shut down only the overheating channel-preserves functionality of the other regulator during localized overloads. |
Applications
| Digital Camera Power Management | Wireless LAN Card Supply |
|---|---|
Use Scenario: Simultaneous powering of CMOS image sensor (1.8V) and ISP processor (3.0V) from single Li-ion cell. IC Role / Device Role / Timing Role: Dual LDO providing isolated, low-noise, sequenced rails with independent shutdown for sensor reset and processor sleep modes. Use Value: 32µVRMS noise ensures clean analog pixel readout; 60mV dropout extends usable battery range to 2.88V for 3.0V rail and 2.4V for 1.8V rail. |
Use Scenario: Regulating 3.0V for WLAN baseband IC and 1.8V for RF transceiver on mini-PCIe card. IC Role / Device Role / Timing Role: Compact dual-regulator replacing discrete solutions-SHDNA/SHDNB synchronize with host suspend/resume signals. Use Value: 70dB PSRR at 10kHz suppresses noise from nearby switching regulators; TDFN package fits tight 3mm × 3mm layout constraints. |
| Notebook Subsystem Power | Handheld Instrument Core Logic |
Use Scenario: Powering embedded controller (3.0V) and touch controller (1.8V) in ultrabook lid assembly. IC Role / Device Role / Timing Role: Dual-output LDO with independent shutdown enables lid-open/closed power state transitions without firmware intervention. Use Value: 115µA per LDO quiescent current minimizes standby drain; thermal shutdown prevents damage during accidental enclosure sealing. |
Use Scenario: Supplying 3.0V to microcontroller and 1.8V to precision ADC in battery-powered multimeter. IC Role / Device Role / Timing Role: Low-noise dual regulator eliminating need for separate LDOs-BP capacitor ensures <32µVRMS noise for 16-bit measurement accuracy. Use Value: Factory-preset voltages eliminate trimming resistors; UCSP option (not this variant) supports <2mm² footprint for handheld size targets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7A2020PDBVR | Single 2.0V output, 300mA, 16µVRMS noise, SOT-23-5 package-lacks dual output and independent shutdown. | Only suitable when system requires one regulated rail; cannot replace dual-voltage sequencing function of MAX8559ETAG2+T. | Select only if redesign allows consolidation of 3.0V/1.8V rails or addition of second regulator. |
| RT9013-30GB | Single 3.0V output, 300mA, 45µVRMS noise, SOT-23-5-no 1.8V rail, no BP pin, no thermal shutdown hysteresis spec. | Cannot support dual-rail architectures; lacks noise-reduction capability needed for sensitive analog sections. | Consider only for cost-sensitive single-rail applications where 32µVRMS noise and thermal hysteresis are noncritical. |
Compared with TPS7A2020PDBVR and RT9013-30GB, the MAX8559ETAG2+T uniquely delivers factory-matched 3.0V/1.8V outputs with independent control, sub-35µVRMS noise, and integrated thermal protection-making it irreplaceable in compact dual-rail portable systems without compromising noise or safety margins.
Availability
MAX8559ETAG2+T is available at Aetrix Electronics and suitable for digital camera modules, wireless LAN cards, notebook embedded controllers, handheld test instruments, and portable medical devices requiring stable component supply across extended temperature ranges (-40°C to +85°C).
Supply support for MAX8559ETAG2+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for demanding industrial, automotive, and portable applications.
The MAX8559 belongs to Maxim's low-noise, dual-LDO product line engineered specifically for battery-powered portable electronics where dual-voltage sequencing, minimal solution size, and ultra-low noise are critical design constraints.
FAQ
What output voltages does the MAX8559ETAG2+T provide?
The MAX8559ETAG2+T provides factory-preset output voltages of 3.0V on OUTA and 1.8V on OUTB. These values are laser-trimmed during production and require no external feedback components. The 'G2' suffix in MAX8559ETAG2+T explicitly denotes this 3.0V/1.8V configuration per Maxim's Output Voltage Selector Guide.
Does the MAX8559ETAG2+T require an external bypass capacitor on the BP pin?
The MAX8559ETAG2+T does not require an external capacitor on the BP pin for basic operation, but adding a 0.01µF ceramic capacitor reduces output noise from 254µVRMS to 32µVRMS. This capacitor forms a low-pass filter with an internal resistor to suppress reference noise-omitting it saves board space but sacrifices low-noise performance.
What is the maximum continuous output current per channel for the MAX8559ETAG2+T?
The MAX8559ETAG2+T delivers up to 300mA of continuous output current per channel (OUTA and OUTB) when using a 4.7µF ceramic output capacitor and operating within its thermal limits. At 150mA, a 2.2µF capacitor suffices. Current limiting activates at 310mA (min), protecting the device during overload or short-circuit conditions.
How does the shutdown functionality work on the MAX8559ETAG2+T?
The MAX8559ETAG2+T features two independent active-low shutdown inputs: SHDNA controls OUTA, and SHDNB controls OUTB. Driving either low disables its respective LDO and discharges the output through a 385Ω internal resistor. Driving both low shuts down the entire IC-including the internal reference-reducing supply current to 0.01µA.
What package type is used for the MAX8559ETAG2+T?
The MAX8559ETAG2+T uses an 8-pin TDFN-EP (3mm × 3mm) package with exposed paddle. The 'T' in the part number indicates TDFN, and the '+T' suffix confirms lead-free finish. The exposed paddle must be soldered to the PCB ground plane to achieve rated 1951mW power dissipation and thermal performance.
MAX8559ETAG2+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 6.5V
- Voltage - Output (Min/Fixed):
- 3V, 1.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.12V @ 100mA, -
- Current - Output:
- 300mA, 300mA
- Current - Quiescent (Iq):
- 290 µA
- Current - Supply (Max):
- -
- PSRR:
- 70dB ~ 54dB (10kHz ~ 100kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TDFN (3x3)
MAX8559ETAG2+T FAQ
1.How can I place an order for MAX8559ETAG2+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8559ETAG2+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8559ETAG2+T reliable?
The price and inventory of MAX8559ETAG2+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8559ETAG2+T is usually 5 days.
3.What payment methods are accepted for MAX8559ETAG2+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8559ETAG2+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8559ETAG2+T?
MAX8559ETAG2+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8559ETAG2+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8559ETAG2+T?
For technical support, including MAX8559ETAG2+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8559ETAG2+T requirements.
6.How does Aetrix verify that MAX8559ETAG2+T is sourced from the original manufacturer or authorized distributors?
All MAX8559ETAG2+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8559ETAG2+T meets industry standards.
7.What is the process for return or replacement of MAX8559ETAG2+T?
All MAX8559ETAG2+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX8559ETAG2+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8559ETAG2+T part is unused and in its original packaging.
Return procedure for MAX8559ETAG2+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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