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Analog Devices Inc./Maxim Integrated MAX8655ETN+TW
- Part No.:
- MAX8655ETN+TW
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package:
- 56-WFQFN Exposed Pad
- Datasheet:
-
MAX8655ETN+TW.pdf
- Description:
- IC REG BUCK ADJ 25A 56TQFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,079
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Product details
Overview
MAX8655ETN+TW from Maxim Integrated is a highly integrated, 25A synchronous PWM buck regulator with internal high- and low-side MOSFETs, operating from 4.5V to 25V input and delivering adjustable 0.7V–5.5V output. It features peak current-mode control, 200kHz–1MHz adjustable switching frequency, monotonic startup into prebiased outputs, and independent overvoltage protection-designed for point-of-load power in servers, telecom, and networking equipment.
For engineers reviewing the MAX8655ETN+TW datasheet, MAX8655ETN+TW pinout, MAX8655ETN+TW application, or MAX8655ETN+TW equivalent, key selection considerations include its 56-pin TQFN package with exposed pad, integrated gate drivers requiring BST/LXB bootstrap configuration, dual current-limit modes (latch-off vs. auto-recovery), 1% FB voltage accuracy over temperature, and 180° phase-shifted SYNCO for multiphase synchronization.
Technical Context
The MAX8655ETN+TW implements peak current-mode control with an externally adjustable oscillator (200kHz–1MHz) and programmable slope compensation (123mV–269mV per switching period). Its dual LDO architecture supplies 5V (AVL) for analog circuitry and 6.5V (VL) for gate drivers, with UVLO at 4.15V AVL threshold and thermal shutdown at +160°C.
Current sensing uses differential inputs (CS+/CS−) with 12× gain and supports two independent limit paths: peak limit set via ILIM1 resistor (e.g., 24kΩ–60kΩ for 27.2A–36.8A), and valley foldback limit set via ILIM2, configurable for latch-off (MODE = AVL) or auto-recovery (MODE = GND). The OVP circuit monitors output independently of FB using a dedicated resistor divider on OVP pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 25A continuous; validated up to 27A RMS per ILX rating and thermal derating curves. |
| Input Voltage Range | 4.5V to 25V; PVIN supports up to 30V absolute max, IN requires ≥4.5V when VL is not bypassed. |
| Output Voltage Range | 0.7V to 5.5V; set by FB divider or external reference (REFIN), with 1% regulation accuracy over -40°C to +85°C. |
| Switching Frequency | 200kHz to 1MHz; set by FSYNC resistor or external clock; synchronized operation supported with 180° phase shift via SYNCO. |
| Current Limit Accuracy | Peak limit: ±12% typical (e.g., 32A ±3.8A at 24kΩ ILIM1); valley limit configurable via ILIM2 resistor with foldback behavior under short-circuit. |
| Thermal Performance | θJC = 3.5°C/W; junction-to-exposed-pad thermal resistance enables high-power dissipation with proper PCB copper area. |
| Startup Behavior | Monotonic rise into prebiased output; soft-start time ≈30.4ms/µF × CSS; no output discharge during startup. |
Pinout & Package
MAX8655ETN+TW is housed in a 56-pin, 8mm × 8mm TQFN package with three exposed pads: PVIN-EP (internally tied to PVIN), LX-EP (tied to LX), and GND-EP (externally connected to system GND). Thermal performance relies on soldering GND-EP to a minimum 200mm² copper pour.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVIN (Pins 1–5, 51–56) | Main power input for high-side MOSFET drain | Connect bulk and ceramic input capacitors directly between PVIN and PGND; PVIN-EP must be soldered to ground plane for thermal conduction. |
| LX (Pins 6, 16–21) | Switch node connecting to external inductor | Pin 6 left unconnected for optimal routing; LX-EP tied internally to LX-critical for high-frequency loop integrity and EMI reduction. |
| PGND (Pins 7–15) | Power ground return for low-side MOSFET source | Must be connected to same copper plane as PVIN decoupling caps; separate from analog GND except at output capacitor negative terminal. |
| AVL (Pin 27) | 5V internal LDO output powering IC core logic | Requires 1µF ceramic cap to GND; supplies REFIN, MODE, OVP, and FB bias; UVLO triggers below 4.15V. |
| VL (Pin 24) | 6.5V internal LDO output powering gate drivers | Requires 2.2µF–10µF ceramic cap to VLGND; connects to IN for VIN < 7V; powers BST charge pump. |
| ILIM1 (Pin 33) | Analog input setting peak current limit threshold | Sources 10µA; resistor to GND sets VILIM1, attenuated 7.5:1 → final CS+–CS− threshold (e.g., 60kΩ → 80mV → ~32A). |
| OVP (Pin 34) | Dedicated overvoltage sense input | Independent of FB network; trip point = 1.15 × nominal FB voltage; latches low-side MOSFET on fault until EN or AVL cycled. |
| SYNCO (Pin 46) | 180° phase-shifted synchronization output | Drives FSYNC of second MAX8655 for interleaved operation; open-drain, level-shifted to AVL; enables true two-phase 50A capability. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Power MOSFETs | Eliminates external high- and low-side switches; reduces BOM count, layout complexity, and trace inductance-induced EMI. |
| Monotonic Startup | Prevents output voltage collapse into prebiased loads-critical for DDR memory, FPGA, and ASIC power sequencing where reverse current must be avoided. |
| Independent Overvoltage Protection | OVP pin senses output via dedicated resistor divider, enabling precise trip points (e.g., 1.2V output → 1.38V OVP) without affecting regulation accuracy or feedback stability. |
| Adjustable Slope Compensation | SCOMP pin accepts 1.25V–2.5V input to scale internal ramp (123–269mV/T), ensuring stable current-mode operation across wide duty-cycle and inductor-value ranges. |
| 180° Phase-Shifted Synchronization | SYNCO output enables true interleaving with second MAX8655, halving input/output ripple current and easing filter design for high-current applications. |
Applications
| Server VR12/VR13 CPU Core Power | Telecom Line Card POL Supply |
|---|---|
|
Use Scenario: Delivering 1.2V/25A to high-performance x86 CPU cores with tight transient response and monotonic startup. IC Role / Device Role / Timing Role: Primary step-down regulator with integrated MOSFETs, programmable soft-start, and POK signaling to CPU reset controller. Use Value: Eliminates need for external power stages; 1% FB accuracy ensures compliance with VR12.0/VR13.0 VOUT tolerance; monotonic start prevents core latch-up on hot-plug. |
Use Scenario: Generating 3.3V/20A for DSP/FPGA on carrier-grade line cards with strict EMI and thermal constraints. IC Role / Device Role / Timing Role: High-efficiency POL converter with external synchronization to backplane clock and thermal shutdown for field reliability. Use Value: 200kHz–1MHz frequency tuning avoids noise bands; 3.5°C/W θJC enables >20A operation on 4-layer board; SYNCO allows multi-rail coherence. |
| DDR Memory VDDQ Supply | Industrial PLC I/O Module Power |
|
Use Scenario: Providing bidirectional 1.5V/15A supply for DDR3/DDR4 VDDQ rails requiring sink capability during termination. IC Role / Device Role / Timing Role: Sourcing/sinking buck regulator with REFIN tracking and adjustable OVP for memory subsystem safety. Use Value: Output sinks current during data bus idle states; REFIN enables tracking to VREF; independent OVP protects memory chips from overvoltage damage. |
Use Scenario: Robust 5V/12A supply for isolated I/O modules operating in extended temperature (-40°C to +85°C) industrial environments. IC Role / Device Role / Timing Role: Wide-input buck regulator with latch-off current limit (MODE = AVL) and thermal shutdown for fault containment. Use Value: 4.5V–25V input range accommodates 12V/24V DC systems; latch-off mode prevents thermal runaway during sustained overload; -40°C to +85°C rating matches PLC requirements. |
Availability
MAX8655ETN+TW is available at Aetrix Electronics and suitable for server VRMs, telecom POL supplies, DDR memory power, industrial PLCs, and networking switch fabric power requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MAX8655ETN+TW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power-management ICs for demanding industrial, communications, and computing applications.
The MAX8655 product line delivers highly integrated, high-current DC-DC regulators targeting space-constrained, thermally challenging point-of-load applications in servers, networking gear, and high-end embedded systems.
FAQ
What is the recommended input capacitor configuration for MAX8655ETN+TW?
Use parallel ceramic capacitors totaling ≥100µF near PVIN pins: one 10µF X7R (0805) per PVIN group (pins 1–5 and 51–56), plus bulk electrolytic/tantalum (47µF–100µF) on the main PVIN rail. All capacitors must connect directly to PGND with minimal trace length to minimize high-frequency loop inductance and ensure stable 25A switching.
How does the MAX8655ETN+TW achieve monotonic startup into a prebiased output?
The MAX8655ETN+TW compares FB voltage against the SS ramp during startup. If FB > SS, both MOSFETs remain off until SS exceeds FB-preventing output discharge. This behavior is hardwired in the control logic and requires no external components, making it reliable for powering precharged FPGA or ASIC rails without damaging downstream devices.
Can MAX8655ETN+TW operate with an input voltage below 4.5V?
Yes-but only if VL is directly connected to IN (per datasheet Figure 11). For VIN < 7V, VL must be wired to IN, and a 10Ω resistor added from VL to AVL. Below 4.5V, operation depends on VL regulation stability and AVL UVLO margin; full 25A capability is not guaranteed below 4.5V due to reduced gate drive headroom.
What is the function of the SCOMP pin on MAX8655ETN+TW, and how should it be configured?
SCOMP sets the internal slope-compensation ramp amplitude (123mV–269mV per switching period) to stabilize current-mode control across duty cycles. Connect SCOMP to AVL for default 250mV/T, to GND for 125mV/T, or to a DAC for dynamic adjustment. Incorrect SCOMP voltage causes subharmonic oscillation or poor transient response-always verify with Bode plot analysis.
How is overvoltage protection implemented independently of the feedback network in MAX8655ETN+TW?
The OVP pin connects to a dedicated resistor divider from VOUT to GND, generating a scaled voltage compared to a 1.15× internal reference. When OVP voltage exceeds threshold, the regulator disables switching and holds the low-side MOSFET on-protecting downstream loads regardless of FB divider accuracy or resistor drift. This is distinct from FB-based regulation and provides fail-safe redundancy.
MAX8655ETN+TW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 56-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 25V
- Voltage - Output (Min/Fixed):
- 0.7V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 25A
- Frequency - Switching:
- 200kHz ~ 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 56-TQFN (8x8)
MAX8655ETN+TW FAQ
1.How can I place an order for MAX8655ETN+TW through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8655ETN+TW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8655ETN+TW reliable?
The price and inventory of MAX8655ETN+TW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8655ETN+TW is usually 5 days.
3.What payment methods are accepted for MAX8655ETN+TW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8655ETN+TW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8655ETN+TW?
MAX8655ETN+TW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8655ETN+TW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8655ETN+TW?
For technical support, including MAX8655ETN+TW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8655ETN+TW requirements.
6.How does Aetrix verify that MAX8655ETN+TW is sourced from the original manufacturer or authorized distributors?
All MAX8655ETN+TW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8655ETN+TW meets industry standards.
7.What is the process for return or replacement of MAX8655ETN+TW?
All MAX8655ETN+TW units undergo pre-shipment inspection (PSI). If there is an issue with MAX8655ETN+TW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8655ETN+TW part is unused and in its original packaging.
Return procedure for MAX8655ETN+TW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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