Analog Devices Inc./Maxim Integrated MAX8660AETL+

Overview

MAX8660AETL+ from Maxim Integrated is a high-efficiency, low-quiescent-current power management IC (PMIC) designed to supply Marvell PXA3xx application processors in smart cellular phones and portable media devices. It integrates four synchronous step-down DC-DC converters (REG1–REG4), four LDO regulators (REG5–REG8), and an always-on 3.3V/30mA LDO (REG8). Key confirmed parameters include 2MHz PWM switching, ±1.5% V3/V4 output voltage accuracy over 0.9V–1.8V range, 1.6A REG3 output current, and 20µA deep-sleep quiescent current.

For engineers reviewing the MAX8660AETL+ datasheet, MAX8660AETL+ pinout, MAX8660AETL+ application, or MAX8660AETL+ equivalent, this page delivers verified technical context for mobile SoC power sequencing, dynamic voltage scaling (DVM), low-battery monitoring, I²C-controlled rail programming, and thermal-safe operation in space-constrained handheld designs.

Technical Context

The MAX8660AETL+ implements a dual-mode PWM/skip control architecture across all four buck converters, enabling automatic transition to high-efficiency light-load operation while supporting forced-PWM mode for noise-sensitive applications. Its DVM capability allows real-time I²C-programmable adjustment of REG3 (VCC_APPS) and REG4 (VCC_SRAM) outputs between 0.725V and 1.8V with 10mV/µs dynamic ramp rate.

Power sequencing is managed via dedicated enable inputs (EN1–EN5, EN34), MR reset input, RSO reset output, and integrated undervoltage/overvoltage lockout (UVLO/OVLO) thresholds at 2.35V (rising) and 6.3V (falling). The device supports Marvell PXA3xx-specific power domain mapping and includes internal off-discharge resistors (550Ω–2kΩ) for controlled rail shutdown.

Key Specifications

Pinout & Package

MAX8660AETL+ uses a 40-pin Thin QFN package (5mm × 5mm × 0.8mm) with exposed thermal pad. Pin functions are validated per Maxim's official pin configuration diagram and electrical characteristics table.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PMIC applications.

Compared with MAX8660ETL+, MAX8660AETL+ removes two regulators to lower cost and power, while retaining full DVM capability for processor core/SRAM rails; versus MAX8661ETL+, it adds the V5 LDO for Marvell PXA3xx multimedia subsystem support without increasing pin count or package size.

Availability

MAX8660AETL+ is available at Aetrix Electronics and suitable for smart cellular phones, personal media players, portable GPS navigation, and digital cameras requiring stable component supply across industrial temperature ranges (-40°C to +85°C).

Supply support for MAX8660AETL+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in analog and mixed-signal ICs for power, sensing, and connectivity applications.

The MAX8660 family targets mobile application processors, delivering integrated power sequencing, dynamic voltage scaling, and battery-aware protection in a single 40-pin QFN package.

FAQ

What is the key functional difference between MAX8660AETL+ and MAX8660ETL+?

The MAX8660AETL+ omits the REG1 step-down converter (VCC_IO) and REG7 linear regulator (VCC_CARD2) present in the MAX8660ETL+. This reduces bill-of-materials cost and quiescent current while retaining identical DVM capability for REG3 (VCC_APPS) and REG4 (VCC_SRAM). Both share the same 40-pin Thin QFN package and pinout, making them layout-compatible where the omitted rails are not used in the target design.

Does MAX8660AETL+ support dynamic voltage scaling for processor core voltage?

Yes, MAX8660AETL+ supports real-time dynamic voltage scaling (DVM) for the REG3 output (V3, labeled VCC_APPS), programmable via I²C from 0.725V to 1.8V in 10mV steps. This feature directly interfaces with Marvell PXA3xx processors to reduce core power during low-activity states. The V3 rail delivers up to 1.6A with ±1.5% accuracy, enabling precise DVFS implementation without external components.

What is the purpose of the V8 pin on MAX8660AETL+ and how is it configured?

The V8 pin on MAX8660AETL+ is the output of REG8, an always-on 3.3V LDO rated for 30mA. It requires no enable signal and remains active even in deep-sleep mode. This rail powers critical backup functions such as real-time clocks, wake-up controllers, and non-volatile memory retention. Its fixed 3.3V output has ±4% tolerance and includes internal off-discharge resistance (1.5kΩ) to ensure controlled discharge during shutdown.

How does the low-battery detection circuit work on MAX8660AETL+?

The MAX8660AETL+ implements a precision low-battery detector with LBF (falling threshold), LBR (rising threshold), and open-drain LBO output. The falling threshold is 1.200V ±18mV, and the rising threshold is 1.250V ±18mV, providing 50mV hysteresis. When battery voltage drops below the falling threshold, LBO asserts low; it deasserts only after voltage rises above the higher rising threshold, preventing oscillation near the trip point during gradual discharge.

Can MAX8660AETL+ operate with a 2.6V input supply?

Yes, MAX8660AETL+ supports an input supply range of 2.6V to 6.0V across all input pins (IN, IN5, IN67, IN8). At 2.6V input, the device remains fully functional with all regulators operational, though dropout margins for higher-output rails (e.g., V1 = 3.3V) decrease. The undervoltage lockout (UVLO) releases at 2.35V (rising), ensuring reliable startup from partially discharged Li-ion cells down to ~2.4V under load.