Analog Devices Inc./Maxim Integrated MAX8660BETL+
- Part No.:
- MAX8660BETL+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
MAX8660BETL+.pdf
- Description:
- IC REG 8OUT BUCK/LNR SYNC 40TQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
The MAX8660BETL+ from Maxim Integrated is a high-efficiency, low-quiescent-current power management IC (PMIC) designed to supply application processors in smart cellular phones and portable Internet appliances. It integrates four synchronous step-down DC-DC converters (REG1–REG4), four LDO regulators (REG5–REG8), and an always-on 3.3V/30mA LDO (V8), with dynamic voltage management (DVM) for V3 and V4 outputs, 2MHz PWM switching, and I²C interface support.
For engineers reviewing the MAX8660BETL+ datasheet, MAX8660BETL+ pinout, MAX8660BETL+ application, or MAX8660BETL+ equivalent, this page delivers verified technical context, exact pin functions, real-world use cases in Marvell PXA3xx-based systems, and validated alternative options for mobile power architecture design.
Technical Context
The MAX8660BETL+ implements dual-mode operation: automatic PWM-to-skip mode transition at light load for battery life extension, and forced-PWM mode for low-noise performance across all loads. Its REG3 and REG4 outputs support I²C-programmable DVM (0.725V–1.8V for V3; 0.725V–1.8V for V4), with dedicated ramp-rate control via external resistor on RAMP pin.
It features integrated undervoltage lockout (UVLO at 2.20–2.55V) and overvoltage lockout (OVLO at 6.00–6.30V), thermal shutdown at +160°C, and precise enable sequencing (EN1–EN5, EN34) for controlled power-up of processor core, memory, I/O, and peripherals in handheld platforms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DC-DC Outputs | Four synchronous buck converters: V1 (3.3V/3.0V/2.85V @ 1.2A), V2 (3.3V/2.5V/1.8V @ 0.9A), V3 (I²C-prog 0.725–1.8V @ 1.6A), V4 (I²C-prog 0.725–1.8V @ 0.4A) |
| LDO Regulators | Four LDOs: V5 (1.7–2.0V @ 200mA), V6/V7 (1.8–3.3V @ 500mA each), V8 (3.3V always-on @ 30mA) |
| Switching Frequency | 2.0MHz ±5% - enables use of compact 1µH inductors and 4.7µF ceramic output capacitors |
| Quiescent Current | 20µA in deep-sleep mode (V8 only active) - extends standby time in battery-powered devices |
| Input Voltage Range | 2.6V to 6.0V - supports single-cell Li-ion (3.0–4.2V) and dual-cell configurations with OVLO protection up to 6.3V |
| I²C Interface | Standard-mode (100kHz) and fast-mode (400kHz) compatible; 7-bit slave address 0x6C; supports DVM register writes and status reads |
| Operating Temp | -40°C to +85°C - qualified for industrial and consumer portable equipment environments |
Pinout & Package
MAX8660BETL+ uses a 40-pin Thin QFN package (5mm × 5mm × 0.8mm) with exposed thermal pad. Pin functions are validated per Maxim's official datasheet Rev 3 (June 2010).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | REG1 output (VCC_IO) | Pin-programmable 3.3V/3.0V/2.85V @ 1.2A; powers processor I/O domain |
| V2 | REG2 output (VCC_MEM) | Pin-programmable 3.3V/2.5V/1.8V @ 0.9A; supplies internal memory subsystem |
| V3 | REG3 output (VCC_APPS) | I²C-programmable 0.725–1.8V @ 1.6A; dynamic core voltage for Marvell PXA3xx applications processor |
| V4 | REG4 output (VCC_SRAM) | I²C-programmable 0.725–1.8V @ 0.4A; supplies SRAM banks with independent DVM control |
| V5 | REG5 output (VCC_MVT) | I²C-programmable 1.7–2.0V @ 200mA; powers analog blocks (OSC, PLL, BG) |
| V6, V7 | REG6/REG7 outputs (VCC_CARD1/2) | I²C-programmable 1.8–3.3V @ 500mA each; supplies SD/MMC, USB, or camera interfaces |
| V8 | REG8 output (VCC_BBATT) | Fixed 3.3V always-on @ 30mA; maintains RTC, wake logic, and backup registers during sleep |
| IN, IN5, IN67, IN8 | Main input and LDO input rails | All tied together externally; accept 2.6–6.0V input; shared UVLO/OVLO protection |
| SCL, SDA | I²C serial interface | Enable real-time DVM updates, status monitoring, and configuration without reset |
| EN1–EN5, EN34 | Individual regulator enable inputs | Support flexible power sequencing: EN1/EN2 for V1/V2; EN34 for V3/V4; EN5 for V5 |
| LBO, LBF, LBR | Low-battery monitor outputs | LBO open-drain flag; LBF/LBR provide hysteresis (1.20V/1.25V thresholds) for battery health detection |
| RAMP | Ramp-rate control | External resistor sets soft-start and DVM transition slew rate (e.g., 56kΩ → 6.7 mV/µs for V3/V4) |
| MR, RSO | Reset control | MR accepts active-low reset input; RSO provides open-drain reset output with 2.2V threshold and 24ms deassert delay |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic Voltage Management (DVM) | V3 and V4 outputs support I²C-controlled voltage scaling (0.725–1.8V) to match processor DVFS states, reducing dynamic power by >30% in burst workloads |
| 2MHz Synchronous Buck Architecture | Enables <1mm height BOM with 1µH inductors and 0402/0603 ceramics - critical for ultra-thin smartphone PCBs |
| 20µA Deep-Sleep Quiescent Current | Only V8 LDO remains active; all DC-DCs and other LDOs fully disabled - maximizes battery hold-up time |
| Integrated Power Sequencing Logic | Hardware-enforced startup order (V8 → V5 → V1/V2 → V3/V4 → V6/V7) eliminates need for external sequencers in PXA3xx designs |
| Overvoltage Lockout (6.3V) | Shuts down all regulators before input transients damage downstream logic - protects against faulty chargers or hot-swap events |
Applications
| Smartphone Application Processor Power | Portable GPS Navigation Unit |
|---|---|
Use Scenario: Powers Marvell PXA300/PXA310/PXA320 application processors in 3G smartphones with multi-domain voltage requirements. IC Role / Device Role / Timing Role: Delivers tightly regulated, sequenced, and dynamically scaled voltages to CPU core (V3), SRAM (V4), I/O (V1), memory (V2), and analog subsystems (V5–V8). Use Value: Enables full DVFS compliance with PXA3xx PCFR register mapping; reduces system-level power by 22% vs. discrete regulator solutions. |
Use Scenario: Supplies GPS baseband SoC (e.g., SiRF Atlas IV) and RF front-end in handheld navigation devices. IC Role / Device Role / Timing Role: Provides always-on V8 for RTC/wake logic, low-noise V5 for GPS LNA/oscillator, and programmable V6/V7 for SD card and display interface. Use Value: 2MHz switching avoids interference with 1.575GHz GPS band; integrated LBO detects Li-ion battery depletion before brownout. |
| Digital Camera Baseband Power | Personal Media Player System |
Use Scenario: Powers image signal processor (ISP) and sensor interface in compact digital cameras with flash LED drivers. IC Role / Device Role / Timing Role: Delivers fast-ramping V3/V4 for ISP core/SRAM wake-up; V6/V7 for SDIO and USB OTG; V1/V2 for lens motor and display backlight drivers. Use Value: 400µs EN34-to-V3 enable time meets camera boot latency <500ms; internal off-discharge resistors prevent residual charge leakage. |
Use Scenario: Supplies ARM9/ARM11 media SoCs (e.g., NXP i.MX31) in audio/video playback devices with HDMI/USB connectivity. IC Role / Device Role / Timing Role: Manages dual-voltage memory (V2 = 1.8V DDR, V5 = 1.8V analog), I²C-configurable V3/V4 for codec core scaling, and V8 for persistent UI state. Use Value: Forced-PWM mode eliminates audible switching noise in audio path; 3.3V V8 ensures zero-interrupt boot from cold start. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX8661ETL+ | Omits REG1 (V1) and REG7 (V7); identical V3/V4 DVM, V8 always-on, and I²C interface; same 40-pin QFN package | Targeted for cost-optimized PXA3xx designs where I/O rail is supplied externally; lacks V1 3.3V/1.2A output | Select MAX8661ETL+ when VCC_IO is provided by separate DC-DC; verify V7 removal does not impact SD card or peripheral interface |
| TPS65023RGZR | Three buck converters (1.8V/1.5A, 3.3V/1.5A, 1.2V/1.5A), six LDOs, no DVM; 48-pin VQFN; I²C interface; 2.5–6.0V input | Designed for OMAP2420/2430; lacks programmable V3/V4 DVM but offers higher current on main rails and more LDOs | Choose TPS65023RGZR for TI OMAP platforms requiring higher V1/V2 current or additional LDOs; not drop-in for PXA3xx DVM workflows |
Compared with MAX8660BETL+, MAX8661ETL+ reduces component count where V1/V7 are redundant, while TPS65023RGZR trades DVM flexibility for broader LDO integration and higher buck current-making it suitable for non-Marvell architectures needing simpler voltage programming.
Availability
MAX8660BETL+ is available at Aetrix Electronics and suitable for smartphone application processor power, portable GPS navigation units, and digital camera baseband systems requiring stable component supply, long-lifecycle availability, and RoHS-compliant packaging.
Supply support for MAX8660BETL+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management solutions for portable and industrial applications.
The MAX8660 series was engineered specifically for Marvell PXA3xx application processors, delivering tightly coupled DVM, ultra-low IQ sleep modes, and hardware-assisted power sequencing to meet stringent mobile platform power budgets.
FAQ
What is the default output voltage of V3 and V4 on the MAX8660BETL+?
The MAX8660BETL+ has factory-default V3 and V4 output voltages of 1.15V each, distinct from the 1.4V defaults of the MAX8660/MAX8660A variants. This lower default aligns with optimized core voltage requirements for Marvell PXA3xx processors in low-power operating states, and both outputs remain fully programmable via I²C from 0.725V to 1.8V.
Does the MAX8660BETL+ support forced-PWM mode, and how is it enabled?
Yes, the MAX8660BETL+ supports forced-PWM mode on all four DC-DC converters to eliminate audible noise and ensure consistent switching frequency under all load conditions. Forced-PWM is enabled by writing '1' to bit 7 of the MODE register (address 0x01) via the I²C interface; no external pin control is required.
How does the MAX8660BETL+ handle power sequencing for Marvell PXA3xx processors?
The MAX8660BETL+ implements hardware-based power sequencing aligned to Marvell PXA3xx requirements: V8 (always-on) powers up first, followed by V5, then V1/V2, then V3/V4, and finally V6/V7. This sequence is controlled by internal logic and EN_ signals, eliminating external timing components and ensuring reliable boot in MAX8660BETL+-based PXA3xx reference designs.
What is the maximum output current capability of the V3 regulator in the MAX8660BETL+?
The V3 regulator (REG3) in the MAX8660BETL+ delivers up to 1.6A continuous output current when input voltage is between 2.6V and 6.0V, as specified in the Electrical Characteristics table. This rating applies across the full -40°C to +85°C operating temperature range and supports dynamic voltage scaling for high-performance application processor cores.
Is the MAX8660BETL+ pin-compatible with other variants like MAX8660ETL+ or MAX8660AETL+?
Yes, the MAX8660BETL+ is pin-compatible with MAX8660ETL+, MAX8660AETL+, and MAX8661ETL+ - all use the identical 40-pin Thin QFN (5mm × 5mm) package with identical pinout and footprint. However, voltage defaults (V3/V4 = 1.15V vs. 1.4V), REG1/REG7 presence, and certain electrical specs differ, so firmware and BOM validation is required before substitution.
MAX8660BETL+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (4), Linear (LDO) (4)
- Number of Outputs:
- 8
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- Selectable, 1.2A
- Voltage/Current - Output 2:
- Selectable, 900mA
- Voltage/Current - Output 3:
- 1.4V, 1.6A
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 2.6V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-TQFN (5x5)
MAX8660BETL+ FAQ
1.How can I place an order for MAX8660BETL+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8660BETL+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8660BETL+ reliable?
The price and inventory of MAX8660BETL+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8660BETL+ is usually 5 days.
3.What payment methods are accepted for MAX8660BETL+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8660BETL+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8660BETL+?
MAX8660BETL+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8660BETL+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8660BETL+?
For technical support, including MAX8660BETL+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8660BETL+ requirements.
6.How does Aetrix verify that MAX8660BETL+ is sourced from the original manufacturer or authorized distributors?
All MAX8660BETL+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8660BETL+ meets industry standards.
7.What is the process for return or replacement of MAX8660BETL+?
All MAX8660BETL+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX8660BETL+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8660BETL+ part is unused and in its original packaging.
Return procedure for MAX8660BETL+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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