Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Analog Devices Inc./Maxim Integrated MAX8805YEWEAA+T

Name: MAX8805YEWEAA+T
Brand: Analog Devices Inc./Maxim Integrated
SKU: MAX8805YEWEAA+T
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MAX8805YEWEAA+T

Manufacturer:: Analog Devices Inc./Maxim Integrated

Category:: Special Purpose Regulators

Package:: 16-WFBGA, WLBGA

Datasheet:: MAX8805YEWEAA+T.pdf

Description:: IC REG CONV WCDMA 1OUT 16WLP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,064

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MAX8805YEWEAA+T from Maxim Integrated is a 2MHz, 600mA high-frequency PWM step-down converter with integrated 60mΩ bypass FET and dual 200mA low-noise LDOs, designed specifically for dynamic power control of WCDMA/NCDMA power amplifiers in mobile handsets. It supports analog voltage positioning via REFIN input (2V/V gain), delivers 7.5µs settling time for 0.8V–3.4V output transitions, and operates from 2.7V–5.5V input.

For engineers reviewing the MAX8805YEWEAA+T datasheet, MAX8805YEWEAA+T pinout, MAX8805YEWEAA+T application, or MAX8805YEWEAA+T equivalent, key selection criteria include its Dual Mode™ bypass activation threshold (0.465 × VIN2), 35µVRMS LDO noise, 70dB PSRR, 0.1µA shutdown current, and 2mm × 2mm UCSP-16 package compatibility with high-density RF front-end layouts.

Technical Context

The MAX8805YEWEAA+T implements a hysteretic PWM control scheme enabling fast transient response and stable operation with minimal external components-only 2.2µF ceramic capacitors required on IN1/IN2 and PA outputs. Its voltage-positioning feedback architecture removes phase lag by sampling LX directly, allowing precise load regulation compensation (−½ × LESR × I_LOAD) without large output capacitance.

Bypass mode is activated either automatically when V_REFIN exceeds 0.465 × V_IN2, or forcibly via the HP logic input, engaging a 60mΩ p-channel MOSFET to connect battery directly to PA terminals. The dual LDOs feature independent enable inputs (EN1/EN2), 200mA guaranteed output, and 70dB PSRR from 10Hz–10kHz.

Key Specifications

Parameter	Value and Actual Design Meaning
Switching Frequency	2MHz - enables use of compact 2.2µF ceramic input/output capacitors and reduces EMI filtering burden in RF-sensitive handset designs.
PA Output Drive	600mA - sufficient for mid-to-high-power WCDMA PA biasing while maintaining thermal margin in 2mm × 2mm WLP package.
REFIN to PA Gain	2V/V - linear analog control allows continuous, noise-immune PA output voltage adjustment from 0.4V to V_BATT.
Bypass FET R_DS(ON)	60mΩ typical - minimizes dropout voltage (<100mV at 90mA) during high-power transmission, extending battery life.
LDO Output Noise	35µV_RMS typical - meets stringent spectral purity requirements for PA bias rails in cellular transceivers.
Shutdown Current	0.1µA - ensures negligible battery drain during phone standby or sleep modes.
Operating Temp Range	−40°C to +85°C - qualified for full industrial temperature operation in handheld consumer electronics.

Pinout & Package

MAX8805YEWEAA+T is housed in a 16-bump, 2mm × 2mm × 0.7mm ultra-thin UCSP (Ultra Compact Silicon Package) with 0.4mm pitch, optimized for space-constrained mobile RF modules.

Pin/Terminal	Circuit Role	Design Meaning
A1: REFBP	Reference noise bypass node	Internal 1.25V bandgap reference output; requires 0.22µF ceramic cap to AGND to suppress LDO output noise.
A2: AGND	Analog ground reference	Low-noise return path for REFBP, REFIN, and LDO feedback; must be isolated from PGND to prevent switching noise coupling.
A3: REFIN	Analog voltage control input	Directly sets PA output voltage as V_PA ≈ 2 × V_REFIN − ½ × L_ESR × I_LOAD; threshold for automatic bypass is 0.465 × V_IN2.
A4: PGND	Power ground for PA converter	High-current return for LX switch and bypass FET; must be connected to system PGND plane with low-inductance path.
B1: LDO2	Second 200mA LDO output	Provides clean bias for auxiliary RF circuitry; individually enabled via EN2; requires local 1µF ceramic bypass.
B2: PA_EN	PA converter enable input	Active-high logic control; drives PA section into 0.1µA shutdown when pulled low; internal pull-down absent.
B3: EN2	LDO2 enable input	Independent logic control for LDO2; connects to IN2 or MCU GPIO; pulls LDO2 output to AGND via 1kΩ when disabled.
B4: LX	Switch node connection	Connects to external 1.5µH inductor; carries high di/dt switching current; requires tight layout to minimize EMI and voltage spikes.
C1: IN2	LDO/reference supply input	2.7V–5.5V input shared by both LDOs and internal reference; bypassed with 2.2µF ceramic to AGND near pin.
C2: HP	Forced bypass mode control	Active-high signal overrides automatic bypass logic; directly activates 60mΩ p-FET to short IN1 to PAA/PAB.
C3/C4: IN1B/IN1A	PA converter supply inputs	Internally tied; accept 2.7V–5.5V battery input; require 2.2µF ceramic bypass to PGND; must match IN2 source.
D1: LDO1	First 200mA LDO output	Primary PA bias rail; output voltage set by factory code (EAA = 1.8V); requires local 1µF ceramic bypass to AGND.
D2: EN1	LDO1 enable input	Independent logic control for LDO1; functions identically to EN2; pulls LDO1 output to AGND via 1kΩ when disabled.
D3/D4: PAB/PAA	PA output terminals	Connected internally to IN1 via bypass FET; carry full PA load current; require 2.2µF ceramic bypass to PGND.

Key Features

Feature	Design Value
Dual Mode™ Bypass Activation	Automatic entry at V_REFIN > 0.465 × V_IN2 prevents ripple-induced instability during voltage scaling, while HP pin enables deterministic forced bypass for burst-mode PA operation.
Voltage-Positioning Feedback	Direct LX sensing eliminates output capacitor phase lag, enabling stable regulation with only 2.2µF ceramic output cap and achieving 7.5µs settling for 0.8V→3.4V transitions.
Integrated Low-Noise LDO Pair	35µV_RMS noise and 70dB PSRR across 10Hz–10kHz allow direct powering of sensitive RF bias circuits without additional filtering.
Ultra-Small UCSP-16 Package	2mm × 2mm × 0.7mm footprint with 0.4mm pitch supports high-density RF module integration and reduces PCB area vs. QFN alternatives.
Dynamic PA Voltage Control	Linear 2V/V REFIN gain enables precise, real-time PA output adjustment from 0.4V to V_BATT, optimizing efficiency across WCDMA transmit power levels.

Applications

WCDMA Power Amplifier Biasing	Cellular Transceiver RF Front-End
Use Scenario: Dynamically adjusting PA supply voltage during WCDMA uplink transmission to match instantaneous power requirements and minimize DC power waste. IC Role / Device Role / Timing Role: Primary PA supply regulator with analog-controlled output and seamless transition between PWM and bypass modes. Use Value: Achieves >60% efficiency at 3.4V output and 500mA load (VIN=3.6V), reducing thermal load and extending talk time.	Use Scenario: Providing ultra-low-noise, independently controlled bias rails for LNA, mixer, and VCO circuits in multi-band cellular transceivers. IC Role / Device Role / Timing Role: Dual-LDO subsystem delivering 1.8V (LDO1) and 2.85V (LDO2) with 70dB PSRR to reject switching noise from adjacent PA converter. Use Value: 35µV_RMS noise ensures <−160dBc/Hz phase noise floor for VCOs, preserving EVM performance in 64-QAM transmissions.
Smartphone Baseband Power Management	NCDMA Handset RF Module
Use Scenario: Consolidating PA supply and auxiliary RF bias generation within a single 2mm × 2mm die area to reduce component count and routing congestion on compact baseband PCBs. IC Role / Device Role / Timing Role: Highly integrated PMIC subsystem combining step-down conversion, bypass FET, and dual LDOs with individual enable controls. Use Value: Eliminates need for discrete bypass MOSFET and two external LDOs, saving ≥5mm² board area and simplifying BOM management.	Use Scenario: Supporting legacy NCDMA handset designs requiring fast PA voltage ramping and low-quiescent-current shutdown during idle periods. IC Role / Device Role / Timing Role: High-speed PA controller with 0.1µA shutdown current and 150µs power-up delay from PA_EN assertion. Use Value: Meets NCDMA 2G/3G coexistence requirements with <100ns timing jitter on PA enable edge and <200mV dropout in bypass mode.

WCDMA Power Amplifier Biasing

Cellular Transceiver RF Front-End

Use Scenario: Dynamically adjusting PA supply voltage during WCDMA uplink transmission to match instantaneous power requirements and minimize DC power waste.

IC Role / Device Role / Timing Role: Primary PA supply regulator with analog-controlled output and seamless transition between PWM and bypass modes.

Use Value: Achieves >60% efficiency at 3.4V output and 500mA load (VIN=3.6V), reducing thermal load and extending talk time.

Use Scenario: Providing ultra-low-noise, independently controlled bias rails for LNA, mixer, and VCO circuits in multi-band cellular transceivers.

IC Role / Device Role / Timing Role: Dual-LDO subsystem delivering 1.8V (LDO1) and 2.85V (LDO2) with 70dB PSRR to reject switching noise from adjacent PA converter.

Use Value: 35µV_RMS noise ensures <−160dBc/Hz phase noise floor for VCOs, preserving EVM performance in 64-QAM transmissions.

Smartphone Baseband Power Management

NCDMA Handset RF Module

Use Scenario: Consolidating PA supply and auxiliary RF bias generation within a single 2mm × 2mm die area to reduce component count and routing congestion on compact baseband PCBs.

IC Role / Device Role / Timing Role: Highly integrated PMIC subsystem combining step-down conversion, bypass FET, and dual LDOs with individual enable controls.

Use Value: Eliminates need for discrete bypass MOSFET and two external LDOs, saving ≥5mm² board area and simplifying BOM management.

Use Scenario: Supporting legacy NCDMA handset designs requiring fast PA voltage ramping and low-quiescent-current shutdown during idle periods.

IC Role / Device Role / Timing Role: High-speed PA controller with 0.1µA shutdown current and 150µs power-up delay from PA_EN assertion.

Use Value: Meets NCDMA 2G/3G coexistence requirements with <100ns timing jitter on PA enable edge and <200mV dropout in bypass mode.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PA power management applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX8805WERExy+T	2.5V/V REFIN-to-PA gain, 650mA output, 2MHz switching frequency	Higher output current and steeper gain slope suit higher-V_PA PA architectures (e.g., 2.85V–3.4V range)	Select when PA requires >600mA or analog control demands finer resolution above 2.5V output.
MAX8805ZERExy+T	2V/V gain, 600mA output, 4MHz switching frequency	Higher switching frequency enables smaller inductors (1.0µH) and lower output ripple at light loads	Select when board space is constrained and EMI filtering must be minimized in high-frequency bands.

Compared with MAX8805WERExy+T, the MAX8805YEWEAA+T offers tighter gain matching for sub-2.5V PA biasing and lower quiescent current in light-load conditions; versus MAX8805ZERExy+T, it trades 4MHz switching for improved heavy-load efficiency and reduced gate-drive losses in battery-limited applications.

Availability

MAX8805YEWEAA+T is available at Aetrix Electronics and suitable for WCDMA/NCDMA handset design, smartphone RF module integration, and cellular transceiver power management requiring stable component supply, RoHS-compliant packaging, and long-term production continuity.

Supply support for MAX8805YEWEAA+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for communications, computing, and consumer electronics.

The MAX8805 family is engineered for dynamic PA power control in cellular handsets, integrating step-down conversion, bypass FET, and dual LDOs to replace discrete solutions while meeting stringent RF noise and thermal constraints.

FAQ

What is the exact output voltage programmed by the 'EAA' suffix in MAX8805YEWEAA+T?

The 'EAA' output voltage code in MAX8805YEWEAA+T specifies a nominal LDO1 output of 1.80V, with guaranteed tolerance of 1.746V to 1.854V at 1mA load and VIN2 = 5.5V. This voltage is factory-trimmed and non-adjustable; LDO2 voltage is selected separately by its own suffix (e.g., 'EBC' = 2.5V). The PA output remains analog-controlled via REFIN and is independent of the EAA coding.

Does MAX8805YEWEAA+T support true 100% duty cycle operation in bypass mode?

Yes, MAX8805YEWEAA+T supports true 100% duty cycle operation: when bypass mode is active (via HP high or automatic threshold), the internal 60mΩ p-channel FET fully connects IN1A/IN1B to PAA/PAB, eliminating switching losses and enabling dropout voltages as low as 60mV at 90mA. During this state, the PWM controller is disabled and LX floats high-impedance.

How does the voltage-positioning feedback in MAX8805YEWEAA+T improve load transient response?

The voltage-positioning feedback in MAX8805YEWEAA+T samples the LX switch node directly (not the PA output), removing phase lag from the output capacitor. This yields an inherently stable loop that responds to load steps within 7.5µs for 0.8V→3.4V transitions, and compensates for inductor DCR drop (−½ × LESR × I_LOAD) to maintain accurate output voltage under varying PA current.

Can MAX8805YEWEAA+T's LDO1 and LDO2 be powered from separate supplies?

No - MAX8805YEWEAA+T requires IN2 to supply both LDOs and the internal reference; IN2 must be connected to the same source as IN1A/IN1B per datasheet guidance. Using separate supplies risks violating absolute maximum ratings on the EN1/EN2 pins and may cause unpredictable LDO behavior due to ground potential differences between AGND and PGND domains.

What is the recommended PCB layout practice for minimizing noise coupling between the PA converter and LDO outputs in MAX8805YEWEAA+T?

To minimize noise coupling, physically separate AGND (pins A2, C1, D1, D2) and PGND (pins A4, C3, C4, D3, D4) planes on the PCB, connecting them at a single point near the device. Route REFBP (A1) and REFIN (A3) traces away from LX (B4) and PAA/PAB (D3/D4), and place their 0.22µF and 2.2µF ceramic bypass capacitors within 2mm of respective pins using dedicated vias to their respective ground planes.

MAX8805YEWEAA+T Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc./Maxim Integrated

Series:: -

Package/Case:: 16-WFBGA, WLBGA

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Applications:: Converter, WCDMA PA Power

Voltage - Input:: 2.7V ~ 5.5V

Number of Outputs:: 1

Voltage - Output:: 0.4V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-WLP

MAX8805YEWEAA+T FAQ

1.How can I place an order for MAX8805YEWEAA+T through Aetrix?

Please submit a Request for Quotation (RFQ) for MAX8805YEWEAA+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MAX8805YEWEAA+T reliable?

The price and inventory of MAX8805YEWEAA+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8805YEWEAA+T is usually 5 days.

3.What payment methods are accepted for MAX8805YEWEAA+T?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8805YEWEAA+T transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MAX8805YEWEAA+T?

MAX8805YEWEAA+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MAX8805YEWEAA+T order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MAX8805YEWEAA+T?

For technical support, including MAX8805YEWEAA+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8805YEWEAA+T requirements.

6.How does Aetrix verify that MAX8805YEWEAA+T is sourced from the original manufacturer or authorized distributors?

All MAX8805YEWEAA+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8805YEWEAA+T meets industry standards.

7.What is the process for return or replacement of MAX8805YEWEAA+T?

All MAX8805YEWEAA+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX8805YEWEAA+T, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MAX8805YEWEAA+T part is unused and in its original packaging.

Return procedure for MAX8805YEWEAA+T:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…