Analog Devices Inc./Maxim Integrated MAX8805YEWEBC+T

Overview

MAX8805YEWEBC+T from Maxim Integrated is a 2MHz, 600mA high-frequency PWM step-down converter with integrated 60mΩ bypass FET and dual 200mA low-noise LDOs, designed specifically for dynamic power control of WCDMA/NCDMA power amplifiers in mobile handsets. It supports analog voltage positioning via REFIN input (2V/V gain), delivers 7.5µs settling time for 0.8V–3.4V output transitions, and operates from 2.7V–5.5V input.

For engineers reviewing the MAX8805YEWEBC+T datasheet, MAX8805YEWEBC+T pinout, MAX8805YEWEBC+T application, or MAX8805YEWEBC+T equivalent, key selection criteria include its Dual Mode™ automatic/forced bypass capability, 35µVRMS LDO noise, 70dB PSRR, 0.1µA shutdown current, and 2mm × 2mm UCSP package compatibility with space-constrained RF front-end designs.

Technical Context

The MAX8805YEWEBC+T implements a hysteretic PWM control scheme enabling fast transient response and stable operation with minimal external components-only 2.2µF ceramic input/output capacitors required. Its voltage-positioning feedback architecture removes phase lag by sampling LX directly, eliminating need for large output capacitance while maintaining tight load regulation.

Dual Mode™ operation integrates both forced bypass (via HP logic input) and automatic bypass (triggered when VREFIN exceeds 0.465 × VIN2), ensuring seamless transition between PWM and direct battery-to-PA conduction. The device uses separate supply domains: IN1A/IN1B powers the PA converter, IN2 powers LDOs and references, isolating sensitive analog circuitry from switching noise.

Key Specifications

Pinout & Package

The MAX8805YEWEBC+T is housed in a 16-bump, 2mm × 2mm × 0.7mm UCSP (Ultra-Compact Silicon Package) with 0.4mm pitch, optimized for high-density RF front-end layouts and reflow-compatible per JEDEC J-STD-020A.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PA power management applications.

Compared with MAX8805WERExy+T and MAX8805ZERExy+T, the MAX8805YEWEBC+T offers optimal balance of 600mA drive capability, 2V/V gain matching common DAC ranges, and 2MHz operation for best-in-class efficiency in mid-power WCDMA PA applications.

Availability

MAX8805YEWEBC+T is available at Aetrix Electronics and suitable for WCDMA handset design, RF front-end module integration, and cellular transceiver power management requiring stable component supply, consistent parametric performance, and long-term production availability.

Supply support for MAX8805YEWEBC+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for communications, computing, and consumer markets.

The MAX8805 family is designed specifically for dynamic PA power control in 3G cellular handsets, integrating step-down conversion, bypass FET, and dual LDOs to replace discrete solutions in space- and efficiency-critical RF power systems.

FAQ

What is the REFIN input voltage range for proper operation of the MAX8805YEWEBC+T?

The MAX8805YEWEBC+T accepts a REFIN input voltage from 0.1V to 2.2V. Within this range, the PA output voltage is linearly regulated as V_OUT = 2 × V_REFIN − ½ × L_ESR × I_LOAD. Operation below 0.4V may trigger undervoltage lockout on internal circuits, and exceeding 2.2V risks violating absolute maximum ratings. For automatic bypass entry, V_REFIN must reach 0.465 × V_IN2.

How does the MAX8805YEWEBC+T achieve 7.5µs output voltage settling time?

The MAX8805YEWEBC+T achieves 7.5µs settling time through its hysteretic PWM control architecture and voltage-positioning feedback. By sampling the LX switch node directly (not the output), the control loop avoids phase lag from output capacitance, enabling immediate correction of load or line transients. Combined with fast 2MHz switching and low-output-impedance bypass FET, it recovers from 0.8V to 3.4V steps within 7.5µs.

Can the LDO1 and LDO2 outputs of the MAX8805YEWEBC+T be used to power RFIC analog blocks?

Yes, the LDO1 and LDO2 outputs of the MAX8805YEWEBC+T are specifically designed for RF-sensitive analog loads. With 35µV_RMS output noise and 70dB PSRR from 10Hz to 10kHz, they meet stringent spectral purity requirements for powering RFIC VCOs, mixers, and ADC reference buffers. Each LDO supports independent enable control and delivers 200mA with <200mV dropout at full load.

What is the purpose of the separate IN1A/IN1B and IN2 supply pins on the MAX8805YEWEBC+T?

The MAX8805YEWEBC+T uses separate supply domains to isolate noise: IN1A/IN1B powers the high-current PA step-down converter and bypass FET, while IN2 powers the low-noise LDOs, bandgap reference, and REFBP/REFIN circuitry. This separation prevents switching noise from IN1 from modulating LDO output or reference accuracy. Both domains must connect to the same battery source but require independent 2.2µF (IN1) and 2.2µF (IN2) ceramic decoupling to their respective grounds (PGND and AGND).

Does the MAX8805YEWEBC+T require external compensation components for stability?

No, the MAX8805YEWEBC+T does not require external compensation components. Its voltage-positioning feedback architecture-sampling the LX node directly-eliminates phase lag introduced by output capacitance, resulting in inherently stable operation. Stability is guaranteed with only 2.2µF ceramic input and output capacitors, and no external resistors or capacitors are needed in the feedback network.