My Inquiry
My Account
Analog Devices Inc./Maxim Integrated MAX8805YEWECC+T
- Part No.:
- MAX8805YEWECC+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Special Purpose Regulators
- Package:
- 16-WFBGA, WLBGA
- Datasheet:
-
MAX8805YEWECC+T.pdf
- Description:
- IC CONV STP-DN PWM 600MA 16WLP
- Quantity:
- Payment:
- Shipping:
Inventory:3,214
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MAX8805YEWECC+T from Maxim Integrated is a 2MHz, 600mA high-frequency step-down converter with dual 200mA low-noise LDOs and integrated 60mΩ bypass FET, designed specifically to dynamically power WCDMA/NCDMA power amplifiers in mobile handsets. It supports analog voltage control (REFIN-to-PA gain = 2V/V), delivers 2.7V output from LDO1/LDO2 (ECC code), operates from 2.7V–5.5V input, and features <35µVRMS noise and 70dB PSRR.
For engineers reviewing the MAX8805YEWECC+T datasheet, MAX8805YEWECC+T pinout, MAX8805YEWECC+T application, or MAX8805YEWECC+T equivalent, key selection considerations include its 2MHz switching frequency, 2V/V REFIN-to-PA gain, 2.7V LDO output (ECC code), bypass-mode dropout performance, and UCSP-16 package compatibility for space-constrained PA power rails.
Technical Context
The MAX8805YEWECC+T implements a hysteretic PWM control scheme enabling fast transient response (<7.5µs settling for 0.8V→3.4V) and stable operation with minimal external components-only 2.2µF ceramic capacitors required on IN1/IN2 and PA outputs. Its voltage-positioning feedback architecture removes phase lag by sampling LX directly, eliminating need for large output capacitance while maintaining tight load regulation.
Bypass mode is activated either automatically when VREFIN exceeds 0.465×VIN2 or forcibly via HP logic input, engaging a 60mΩ p-channel MOSFET to connect battery directly to PA output. Dual LDOs operate independently with individual EN1/EN2 controls, each delivering 200mA at 35µVRMS noise and 70dB PSRR across 10Hz–10kHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switching Frequency | 2MHz - enables use of compact 2.2µF ceramic input/output capacitors and reduces EMI filtering burden. |
| PA Output Drive | 600mA - sufficient for mid-power WCDMA/NCDMA PA stages without thermal derating in 2mm×2mm package. |
| REFIN-to-PA Gain | 2V/V - linear analog control allows precise, continuous PA voltage adjustment from 0.4V to VBATT using external DAC. |
| LDO Output Voltage (ECC) | 2.7V ±3% - factory-trimmed dual LDOs provide stable bias for PA driver stages with guaranteed 200mA drive capability. |
| Bypass FET RDS(ON) | 60mΩ typ - minimizes dropout and conduction loss during high-power transmission, extending battery life. |
| LDO Noise | 35µVRMS - ultra-low noise ensures clean bias for sensitive RF front-end circuitry without added filtering. |
| Shutdown Current | 0.1µA - enables deep sleep modes in handset baseband processors to conserve standby power. |
Pinout & Package
MAX8805YEWECC+T is housed in a 16-bump, 2mm × 2mm × 0.7mm UCSP (Ultra Compact Silicon Package) with 4×4 bump grid, optimized for ultra-thin mobile handset PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1: REFBP | Reference noise bypass node | Internal 1.25V bandgap reference output; must be decoupled with 0.22µF ceramic to AGND to suppress LDO output noise. |
| A2: AGND | Analog ground reference | Low-noise return path for REFBP, REFIN, LDOs; must be isolated from PGND and connected via single-point star ground. |
| A3: REFIN | Analog control input for PA output | Directly sets PA output voltage as VPA ≈ 2 × VREFIN; automatic bypass triggers at 0.465 × VIN2. |
| A4: PGND | Power ground for PA converter | High-current return for LX, PAA/PAB, IN1A/IN1B; requires dedicated copper pour separate from AGND. |
| B1: LDO2 | Second 200mA LDO output | Provides 2.7V (ECC code) bias; requires local 1µF ceramic capacitor to AGND for stability and PSRR optimization. |
| B2: PA_EN | Enable control for PA converter | Active-high logic input; drives PA converter into shutdown (0.1µA IQ) when pulled low or grounded. |
| B3: EN2 | Enable control for LDO2 | Independent logic enable for LDO2; allows dynamic power gating of second PA bias rail. |
| B4: LX | Switch node for PA inductor | Connects to external 1.5µH inductor; carries high di/dt switching current; requires short, low-inductance layout. |
| C1: IN2 | Supply input for LDOs & reference | 2.7V–5.5V input shared with IN1A/IN1B; requires 2.2µF ceramic bypass to AGND near pin. |
| C2: HP | Forced bypass mode control | Active-high input that immediately engages 60mΩ bypass FET, overriding automatic threshold behavior. |
| C3/C4: IN1B/IN1A | PA converter supply inputs | Internally shorted; accept same 2.7V–5.5V battery source as IN2; require local 2.2µF ceramic to PGND. |
| D1: LDO1 | First 200mA LDO output | Delivers 2.7V (ECC code); identical specs to LDO2; requires 1µF ceramic bypass to AGND. |
| D2: EN1 | Enable control for LDO1 | Independent logic enable for LDO1; supports staggered power-up sequencing in multi-rail PA subsystems. |
| D3/D4: PAB/PAA | PA output terminals in bypass mode | Internally connected to IN1A/IN1B via bypass FET; require 2.2µF ceramic bypass to PGND for ripple suppression. |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic PA voltage control | Linear 2V/V gain from 0.4V–2.2V REFIN enables precise, real-time PA power adjustment without digital interface overhead. |
| Ultra-fast load transient response | 7.5µs settling time for 0.8V→3.4V output change maintains PA linearity during rapid modulation bursts in WCDMA. |
| Voltage-positioning feedback | Direct LX sensing eliminates output capacitor phase lag, allowing stable regulation with only 2.2µF ceramic output cap. |
| Dual independent LDOs | Each delivers 200mA at 35µVRMS noise and 70dB PSRR, enabling clean, separately controllable bias for PA driver and pre-driver stages. |
| Auto/forced bypass mode | Automatic entry at 0.465×VIN2 or HP-driven forced mode ensures seamless transition to low-dropout battery coupling during peak transmit power. |
Applications
| WCDMA Power Amplifier Supply | Smartphone RF Front-End Bias |
|---|---|
Use Scenario: Dynamically adjusting PA supply voltage across WCDMA transmit power levels (0–24dBm) to maximize efficiency and minimize heat. IC Role / Device Role / Timing Role: Primary PA supply regulator with analog-controlled output and seamless bypass mode for high-power bursts. Use Value: Reduces average PA power dissipation by >30% vs. fixed-supply architectures, extending talk time and lowering thermal stress on antenna modules. | Use Scenario: Providing clean, independently enabled bias rails to multiple RF ICs (e.g., PA driver + pre-driver) in compact smartphone layouts. IC Role / Device Role / Timing Role: Dual-LDO subsystem delivering 2.7V bias with 35µVRMS noise and 70dB PSRR for sensitive RF signal paths. Use Value: Eliminates need for discrete LDOs and external noise filters, saving >3mm² PCB area while meeting ACPR and EVM requirements. |
| NCDMA Handset Transmitter | Wireless PDA RF Power Management |
Use Scenario: Supporting NCDMA CDMA2000 1xRTT transmit envelopes requiring fast PA voltage slewing and low-noise bias. IC Role / Device Role / Timing Role: High-bandwidth step-down converter with 7.5µs output settling and dual-LDO bias generation. Use Value: Maintains adjacent channel leakage ratio (ACLR) compliance during rapid power ramping, avoiding spectral regrowth. | Use Scenario: Enabling compact, battery-efficient RF power delivery in handheld PDAs with limited board space and thermal headroom. IC Role / Device Role / Timing Role: Integrated PA supply + dual bias solution in 2mm×2mm UCSP package with minimal external components. Use Value: Achieves full RF functionality in sub-8mm-thick form factors without compromising PA efficiency or noise performance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PA power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX8805WERExy+T | 2.5V/V REFIN-to-PA gain, 650mA output, same 2MHz switching frequency and UCSP-16 package. | Requires higher REFIN voltage (e.g., 1.08V for 2.7V PA output) and delivers 50mA more current; suitable where higher PA drive is needed. | Select when PA load exceeds 600mA or system DAC supports 0.72V–1.76V REFIN range. |
| MAX8805ZERExy+T | 2V/V gain like MAX8805YEWECC+T but 4MHz switching frequency, same 600mA rating and UCSP-16 package. | Enables smaller inductors/caps (e.g., 1.0µH) and lower output ripple at cost of ~3% efficiency reduction at medium loads. | Select when board area is constrained and 4MHz operation aligns with system EMI requirements. |
Compared with MAX8805WERExy+T, MAX8805YEWECC+T provides tighter REFIN voltage range for 2.7V PA output and matches typical WCDMA PA current demands; versus MAX8805ZERExy+T, it trades higher efficiency at 2MHz for relaxed EMI filter design and proven thermal performance in thin handset assemblies.
Availability
MAX8805YEWECC+T is available at Aetrix Electronics and suitable for WCDMA/NCDMA handset design, smartphone RF front-end development, and wireless PDA power management requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for MAX8805YEWECC+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for portable, industrial, and communications systems.
The MAX8805 family is engineered for dynamic PA power delivery in cellular handsets, integrating step-down conversion, bypass FET, and dual LDOs in one ultra-compact UCSP to eliminate discrete solutions and optimize RF efficiency.
FAQ
What is the exact output voltage of the LDOs in MAX8805YEWECC+T?
The MAX8805YEWECC+T features two factory-trimmed LDOs both set to 2.7V nominal output (ECC code), with guaranteed tolerance of ±3% (2.619V to 2.781V) across temperature and load. This voltage is specified at VIN2 = 5.5V/3.4V and ILDO = 1mA/100mA, and remains stable due to 70dB PSRR and 35µVRMS noise performance.
How does the bypass mode function in MAX8805YEWECC+T?
The MAX8805YEWECC+T supports both automatic and forced bypass modes. Automatic bypass activates when VREFIN exceeds 0.465 × VIN2, connecting IN1A/IN1B directly to PAA/PAB via a 60mΩ internal p-channel FET. Forced bypass is triggered by driving the HP pin high. In either case, the step-down converter enters 100% duty cycle, minimizing dropout and maximizing battery-to-PA efficiency during high-power transmission.
What is the REFIN-to-PA voltage gain for MAX8805YEWECC+T?
The MAX8805YEWECC+T has a fixed REFIN-to-PA gain of 2V/V, meaning the PA output voltage approximates VPA = 2 × VREFIN − ½ × LESR × ILOAD. For a target 2.7V PA output, VREFIN should be set to ~1.35V (adjusted for inductor DCR). This gain is specific to the Y/Z variants and differs from the 2.5V/V gain used in W/X variants.
Which package type is used by MAX8805YEWECC+T?
The MAX8805YEWECC+T uses a 16-bump Ultra Compact Silicon Package (UCSP) measuring 2mm × 2mm × 0.7mm with a 4×4 bump grid. This lead-free, RoHS-compliant package is optimized for ultra-thin mobile handset PCBs and requires JEDEC J-STD-020A-compliant reflow profiles with preheating.
Does MAX8805YEWECC+T support independent control of its two LDOs?
Yes, MAX8805YEWECC+T provides fully independent control of its dual 200mA LDOs via separate enable pins: EN1 controls LDO1 and EN2 controls LDO2. Each LDO can be powered up/down individually, supporting flexible power sequencing, dynamic bias scaling, and fault-isolation strategies in multi-stage PA architectures without affecting the other LDO or the main step-down converter.
MAX8805YEWECC+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-WFBGA, WLBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Converter, WCDMA PA Power
- Voltage - Input:
- 2.7V ~ 5.5V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.4V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLP
MAX8805YEWECC+T FAQ
1.How can I place an order for MAX8805YEWECC+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8805YEWECC+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8805YEWECC+T reliable?
The price and inventory of MAX8805YEWECC+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8805YEWECC+T is usually 5 days.
3.What payment methods are accepted for MAX8805YEWECC+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8805YEWECC+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8805YEWECC+T?
MAX8805YEWECC+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8805YEWECC+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8805YEWECC+T?
For technical support, including MAX8805YEWECC+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8805YEWECC+T requirements.
6.How does Aetrix verify that MAX8805YEWECC+T is sourced from the original manufacturer or authorized distributors?
All MAX8805YEWECC+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8805YEWECC+T meets industry standards.
7.What is the process for return or replacement of MAX8805YEWECC+T?
All MAX8805YEWECC+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX8805YEWECC+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8805YEWECC+T part is unused and in its original packaging.
Return procedure for MAX8805YEWECC+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX8805YEWECC+T Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
