Analog Devices Inc./Maxim Integrated MAX8805YEWEEE+T
- Part No.:
- MAX8805YEWEEE+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Special Purpose Regulators
- Package:
- 16-WFBGA, WLBGA
- Datasheet:
-
MAX8805YEWEEE+T.pdf
- Description:
- IC REG CONV WCDMA 1OUT 16WLP
- Quantity:
- Payment:

- Shipping:

Inventory:3,966
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MAX8805YEWEEE+T from Maxim Integrated is a 2MHz, 600mA high-frequency step-down converter with dual 200mA low-noise LDOs and integrated 60mΩ bypass FET, designed specifically to dynamically power WCDMA/NCDMA power amplifiers in mobile handsets. It supports analog voltage control (REFIN-to-PA gain = 2V/V), delivers 7.5µs settling time for 0.8V–3.4V output transitions, and operates from 2.7V–5.5V input.
For engineers reviewing the MAX8805YEWEEE+T datasheet, MAX8805YEWEEE+T pinout, MAX8805YEWEEE+T application, or MAX8805YEWEEE+T equivalent, key selection criteria include its Dual Mode™ automatic bypass threshold (0.465 × VIN2), 35µVRMS LDO noise, 70dB PSRR, 0.1µA shutdown current, and 2mm × 2mm UCSP package compatibility with space-constrained RF front-end designs.
Technical Context
The MAX8805YEWEEE+T implements a hysteretic PWM control scheme enabling fast transient response and stable operation with only 2.2µF ceramic input/output capacitors. Its voltage-positioning feedback-sampling LX directly-eliminates phase lag from output capacitance, allowing ultra-small external components while maintaining tight regulation.
Dual independent LDOs (LDO1/LDO2) each deliver 200mA with 35µVRMS noise and 70dB PSRR (10Hz–10kHz), individually enabled via EN1/EN2 logic inputs. Bypass mode is triggered either automatically when VREFIN exceeds 0.465 × VIN2 or forced via HP pin, engaging the 60mΩ p-channel FET to connect battery directly to PA outputs PAA/PAB.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switching Frequency | 2MHz - enables use of compact 2.2µF ceramic input/output capacitors and reduces EMI filtering burden |
| PA Converter Output Drive | 600mA - sufficient for mid-to-high-power WCDMA PA biasing under dynamic load conditions |
| REFIN-to-PA Gain | 2V/V - linear analog control allows precise, continuous PA output voltage adjustment from 0.4V to VBATT |
| LDO Output Noise | 35µVRMS (100Hz–100kHz) - ensures clean bias for sensitive RF power amplifier stages |
| Bypass FET RDS(ON) | 60mΩ (typ) - minimizes dropout and conduction loss during high-power transmission bursts |
| Shutdown Current | 0.1µA - preserves battery life during idle or sleep states in portable handset applications |
| Operating Input Range | 2.7V to 5.5V - compatible with single-cell Li-ion (3.0–4.2V) and boosted supply rails |
Pinout & Package
MAX8805YEWEEE+T is housed in a 16-bump, 2mm × 2mm × 0.7mm UCSP (Ultra Compact Silicon Package) with 4×4 bump grid, optimized for ultra-thin mobile handset PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 REFBP | Reference noise bypass | Internal bandgap reference decoupling node; requires 0.22µF ceramic cap to AGND to suppress LDO output noise |
| A2 AGND | Analog ground | Low-noise return path for REFBP, REFIN, LDOs; must be isolated from PGND to prevent switching noise coupling |
| A3 REFIN | PA output voltage control input | Analog DAC-driven input setting PA output as 2 × VREFIN; also triggers automatic bypass at 0.465 × VIN2 |
| A4 PGND | Power ground | High-current return for PA step-down converter and bypass FET; separate from AGND to avoid ground bounce |
| B1 LDO2 | LDO2 output | 200mA low-noise regulated output; requires local 1µF ceramic capacitor to AGND |
| B2 PA_EN | PA converter enable | Active-high logic input; pull low to disable step-down stage and enter 0.1µA shutdown state |
| B3 EN2 | LDO2 enable | Independent active-high control for LDO2; allows selective powering of PA bias rails |
| B4 LX | Switch node | Connection to external inductor; carries high di/dt switching current; layout critical for EMI and efficiency |
| C1 IN2 | LDO/reference supply | Input for LDO1, LDO2, and internal reference; must tie to same source as IN1A/IN1B and bypass with 2.2µF |
| C2 HP | Forced bypass mode | Active-high input to immediately engage 60mΩ bypass FET, overriding automatic threshold behavior |
| C3/C4 IN1B/IN1A | PA converter input | Parallel-connected battery inputs for PA stage; require shared 2.2µF ceramic bypass to PGND |
| D1 LDO1 | LDO1 output | 200mA low-noise regulated output; requires local 1µF ceramic capacitor to AGND |
| D2 EN1 | LDO1 enable | Independent active-high control for LDO1; enables flexible sequencing and power domain isolation |
| D3/D4 PAB/PAA | PA output terminals | Direct connection points to power amplifier; internally tied to IN1_ in bypass mode; bypass with 2.2µF to PGND |
Key Features
| Feature | Design Value |
|---|---|
| Dual Mode™ Bypass Control | Automatic entry at VREFIN > 0.465 × VIN2 + forced activation via HP pin ensures optimal efficiency across full PA power range |
| Voltage-Positioning Feedback | Direct LX sampling eliminates output-capacitor phase lag, enabling stable regulation with ≤2.2µF ceramic output caps |
| 7.5µs Output Settling Time | Enables rapid PA power level changes between WCDMA transmit slots without overshoot or droop |
| Individual LDO Enable Logic | Separate EN1/EN2 pins allow independent on/off control of LDO1 and LDO2 for dynamic PA bias sequencing |
| Ultra-Low Shutdown Current | 0.1µA quiescent draw extends standby battery life in always-on mobile communication devices |
Applications
| WCDMA Power Amplifier Supply | RF Front-End Bias Management |
|---|---|
Use Scenario: Dynamically adjusting PA supply voltage during WCDMA uplink transmission to optimize linearity and efficiency across varying output power levels. IC Role / Device Role / Timing Role: Primary PA supply regulator with analog-controlled output and seamless transition between PWM and bypass modes. Use Value: Achieves >90% efficiency at high output currents in bypass mode while maintaining <10mV ripple in PWM mode for clean RF envelope tracking. | Use Scenario: Providing low-noise, independently controllable bias voltages to multiple RF ICs (e.g., driver amps, switches) in smartphone transceiver modules. IC Role / Device Role / Timing Role: Dual-LDO subsystem delivering 2.85V/2.85V bias rails with 35µVRMS noise and 70dB PSRR for signal integrity. Use Value: Eliminates need for discrete LDOs and external noise filters, reducing BOM count and PCB area by >30% versus discrete solutions. |
| Smartphone Transmitter Optimization | NCDMA Handset Power Management |
Use Scenario: Supporting envelope-tracking architectures where PA supply must respond within microseconds to baseband DAC commands. IC Role / Device Role / Timing Role: Fast-settling (7.5µs), analog-input-controlled step-down converter synchronized to LTE/WCDMA slot timing. Use Value: Enables real-time PA supply modulation matching instantaneous RF power demand, improving ACPR and power-added efficiency. | Use Scenario: Managing battery-to-PA power delivery in legacy NCDMA handsets requiring high peak current bursts with minimal voltage droop. IC Role / Device Role / Timing Role: High-current (600mA) step-down + bypass FET co-located with PA to minimize trace inductance and IR drop. Use Value: 60mΩ bypass FET sustains >1A peak current with <60mV dropout, extending talk time and preventing transmit clipping. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PA power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX8805WEREE+T | 2.5V/V REFIN-to-PA gain, 650mA output drive, same 2MHz switching frequency and UCSP package | Better suited for systems requiring higher PA output voltage scaling (e.g., 0.72V REFIN → 1.8V PA); slightly higher current capability | Select when PA voltage range exceeds 3.4V or when >600mA sustained current is required |
| MAX8805ZEREE+T | 4MHz switching frequency, 2V/V gain, same 600mA rating and UCSP package; higher switching loss but smaller external components | Preferred for ultra-compact layouts where inductor/capacitor footprint is constrained more than efficiency | Select when board area is prioritized over peak efficiency, especially in sub-3mm² RF module designs |
Compared with MAX8805WEREE+T and MAX8805ZEREE+T, the MAX8805YEWEEE+T offers the optimal balance of 2V/V analog control linearity, 600mA drive, and 2MHz operation-making it ideal for mainstream WCDMA handset platforms where efficiency, noise, and layout simplicity are equally critical.
Availability
MAX8805YEWEEE+T is available at Aetrix Electronics and suitable for WCDMA/NCDMA handset design, smartphone RF front-end development, and portable wireless PDA power management requiring stable component supply, RoHS-compliant packaging, and production-ready lead times.
Supply support for MAX8805YEWEEE+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for communications, computing, and consumer electronics.
The MAX8805 family was engineered specifically for dynamic PA power delivery in 3G cellular handsets, integrating step-down conversion, bypass FET, and dual LDOs into a single 2mm × 2mm UCSP to eliminate discrete power rail complexity.
FAQ
What is the REFIN-to-PA output voltage gain for MAX8805YEWEEE+T?
The MAX8805YEWEEE+T features a fixed 2V/V REFIN-to-PA output voltage gain. When a 0.9V analog voltage is applied to REFIN, the PA output regulates to approximately 1.8V (accounting for voltage-positioning load regulation). This ratio is confirmed in the Electrical Characteristics table and applies across the full -40°C to +85°C operating range.
Does MAX8805YEWEEE+T support automatic bypass mode, and what triggers it?
Yes, MAX8805YEWEEE+T supports automatic bypass mode, which engages when the REFIN voltage exceeds 0.465 × VIN2 (e.g., at 1.67V when VIN2 = 3.6V). This threshold includes 50mV hysteresis to prevent oscillation near the transition point. The feature is documented in the Dual Mode™ Threshold specification and Figure 2 of the datasheet.
What are the recommended output capacitors for the PA step-down converter in MAX8805YEWEEE+T?
The MAX8805YEWEEE+T is optimized for 2.2µF ceramic capacitors on both input (IN1A/IN1B) and output (PAA/PAB) nodes. This value is validated in the Typical Operating Characteristics and explicitly cited in the General Description for maintaining low ripple and stability with fast transient response.
How does the voltage-positioning feedback architecture improve load regulation in MAX8805YEWEEE+T?
The MAX8805YEWEEE+T samples the LX switch node directly (not the PA output) for feedback, removing phase lag from the output capacitor. Combined with resistor R3 in the feedback network, this yields load regulation equal to half the inductor's series resistance times load current-reducing output droop during PA current surges and minimizing overshoot during voltage transitions.
Can LDO1 and LDO2 in MAX8805YEWEEE+T be powered down independently?
Yes, MAX8805YEWEEE+T provides independent enable control: EN1 controls LDO1 and EN2 controls LDO2. Each pin is active-high and can be driven separately to sequence bias rails or disable unused regulators-confirmed in the Pin Description table and Electrical Characteristics section for shutdown output impedance.
MAX8805YEWEEE+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-WFBGA, WLBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Converter, WCDMA PA Power
- Voltage - Input:
- 2.7V ~ 5.5V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.4V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLP
MAX8805YEWEEE+T FAQ
1.How can I place an order for MAX8805YEWEEE+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8805YEWEEE+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8805YEWEEE+T reliable?
The price and inventory of MAX8805YEWEEE+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8805YEWEEE+T is usually 5 days.
3.What payment methods are accepted for MAX8805YEWEEE+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8805YEWEEE+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8805YEWEEE+T?
MAX8805YEWEEE+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8805YEWEEE+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8805YEWEEE+T?
For technical support, including MAX8805YEWEEE+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8805YEWEEE+T requirements.
6.How does Aetrix verify that MAX8805YEWEEE+T is sourced from the original manufacturer or authorized distributors?
All MAX8805YEWEEE+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8805YEWEEE+T meets industry standards.
7.What is the process for return or replacement of MAX8805YEWEEE+T?
All MAX8805YEWEEE+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX8805YEWEEE+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8805YEWEEE+T part is unused and in its original packaging.
Return procedure for MAX8805YEWEEE+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAX8805YEWEEE+T Tags

-
TPS51206DSQR
Texas Instruments

-
TPS51200DRCR
Texas Instruments

-
TPS51200DRCT
Texas Instruments

-
TPS62740DSSR
Texas Instruments

-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi

-
RT9026GSP
Richtek USA Inc.

-
LP2998MRX/NOPB
Texas Instruments

-
TPS51200QDRCRQ1
Texas Instruments

-
DPA423GN-TL
Power Integrations

-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
