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Analog Devices Inc./Maxim Integrated MAX8805YEWEGG+T
- Part No.:
- MAX8805YEWEGG+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Special Purpose Regulators
- Package:
- 16-WFBGA, WLBGA
- Datasheet:
-
MAX8805YEWEGG+T.pdf
- Description:
- IC CONV STP-DN PWM 600MA 16WLP
- Quantity:
- Payment:
- Shipping:
Inventory:4,240
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Product details
Overview
MAX8805YEWEGG+T from Maxim Integrated is a 2MHz, 600mA high-frequency step-down converter with dual 200mA low-noise LDOs and integrated 60mΩ bypass FET, designed specifically to dynamically power WCDMA/NCDMA power amplifiers in mobile handsets. It supports analog DAC-controlled output voltage (0.4V–VBATT), achieves 7.5µs settling time for 0.8V→3.4V transitions, and operates from 2.7V–5.5V input.
For engineers reviewing the MAX8805YEWEGG+T datasheet, MAX8805YEWEGG+T pinout, MAX8805YEWEGG+T application, or MAX8805YEWEGG+T equivalent, key selection criteria include REFIN-to-PA gain (2V/V), bypass-mode on-resistance (60mΩ typ), LDO noise (35µVRMS typ), thermal shutdown (+160°C), and UCSP-16 package compatibility with 2mm × 2mm PCB footprints.
Technical Context
The MAX8805YEWEGG+T implements a hysteretic PWM control scheme enabling fast transient response and stable operation with minimal external components-only 2.2µF ceramic capacitors required on IN1A/IN1B and output. Its voltage-positioning feedback architecture removes phase lag by sampling LX directly, eliminating need for large output capacitance while maintaining tight load regulation.
Dual-mode operation integrates seamless transition between PWM step-down (for medium/low-power PA states) and forced/automatic bypass (for high-power transmission). Automatic bypass triggers at VREFIN > 0.465 × VIN2, using VIN2-not VIN1-to avoid switching noise false triggering, and HP logic input enables direct bypass activation independent of REFIN.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switching Frequency | 2MHz - enables use of compact 2.2µF ceramic input/output capacitors and reduces EMI filtering burden. |
| REFIN to PA Gain | 2V/V - linear DAC control allows precise, continuous PA output voltage adjustment from 0.4V to VBATT. |
| Bypass FET RDS(ON) | 60mΩ typical - minimizes dropout and conduction loss during high-current PA transmission bursts. |
| LDO Output Noise | 35µVRMS typical - ensures clean bias for sensitive RF power amplifier stages without added filtering. |
| Shutdown Current | 0.1µA - preserves battery life in standby mode for portable handset applications. |
| Input Voltage Range | 2.7V to 5.5V - compatible with single-cell Li-ion (3.0–4.2V) and multi-cell or boosted supply rails. |
| Thermal Shutdown | +160°C with 20°C hysteresis - protects device under sustained overload or poor PCB thermal design. |
Pinout & Package
The MAX8805YEWEGG+T is housed in a 16-bump, 2mm × 2mm × 0.7mm ultra-thin UCSP (Ultra Compact Silicon Package) with 4×4 bump grid, optimized for space-constrained mobile handset PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1: REFBP | Reference noise bypass | Internal bandgap reference decoupling node; requires 0.22µF ceramic cap to AGND for LDO noise reduction. |
| A2: AGND | Analog ground | Low-noise return path for internal reference, LDOs, and REFIN; must be isolated from PGND to prevent coupling. |
| A3: REFIN | DAC-controlled input | Analog voltage sets PA output (VPA_ = 2 × VREFIN); also triggers automatic bypass when >0.465 × VIN2. |
| A4: PGND | Power ground | High-current return for PA step-down switch node (LX) and bypass FET; separate from AGND to limit noise injection. |
| B1: LDO2 | LDO2 output | 200mA low-noise regulated output; requires local 1µF ceramic cap to AGND for stability and PSRR performance. |
| B2: PA_EN | PA converter enable | Active-high logic input; drives to GND disables entire step-down converter and places LX in high-Z state. |
| B3: EN2 | LDO2 enable | Independent logic control for LDO2; shutdown pulls output impedance to 1kΩ and disables regulator. |
| B4: LX | Switch node | Connection to external inductor; carries high di/dt PWM current; layout critical for EMI and efficiency. |
| C1: IN2 | LDO/reference supply | 2.7–5.5V input for LDOs and internal reference; must tie to same source as IN1A/IN1B and bypass with 2.2µF cap. |
| C2: HP | Forced bypass control | Active-high logic input that directly activates bypass FET regardless of REFIN level or duty cycle. |
| C3/C4: IN1B/IN1A | PA converter input | Parallel-connected 2.7–5.5V inputs for main PA rail; internally joined; require shared 2.2µF ceramic bypass to PGND. |
| D1: LDO1 | LDO1 output | 200mA low-noise regulated output; identical bypass and layout requirements as LDO2. |
| D2: EN1 | LDO1 enable | Independent logic control for LDO1; functionally identical to EN2 but for LDO1. |
| D3/D4: PAB/PAA | PA output terminals | Output nodes connected to PA load; internally tied to IN1A/IN1B via bypass FET; require 2.2µF ceramic caps to PGND. |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic PA voltage control | Linear 0.4V–VBATT output range via analog REFIN input enables real-time WCDMA power backoff without digital interface overhead. |
| Ultrafast settling time | 7.5µs typical for 0.8V→3.4V transitions ensures rapid PA power-state changes compliant with WCDMA envelope tracking timing. |
| Dual independent LDOs | Two 200mA, 35µVRMS-noise LDOs with individual EN1/EN2 pins allow selective biasing of PA driver and pre-driver stages. |
| Hysteretic PWM architecture | Eliminates external compensation and enables stable operation with only 2.2µF ceramic output capacitors-no electrolytics needed. |
| Voltage-positioning feedback | Direct LX sensing compensates for inductor DCR drop, reducing load transient overshoot and improving accuracy across current range. |
Applications
| WCDMA Power Amplifier Supply | RF Front-End Bias Management |
|---|---|
Use Scenario: Dynamically powering the final-stage power amplifier in 3G WCDMA handsets during varying transmit power levels (e.g., 0–24dBm). IC Role / Device Role / Timing Role: Primary PA supply IC delivering regulated VPA_ with analog REFIN-based voltage positioning and seamless bypass mode switching. Use Value: Enables >90% peak efficiency in bypass mode and <2% gain error in PWM mode, extending talk time while meeting stringent ACLR specs. | Use Scenario: Providing clean, low-noise bias voltages to RF driver and pre-driver stages adjacent to the main PA. IC Role / Device Role / Timing Role: Dual LDO subsystem supplying independently enabled 2.85V outputs (e.g., VLDO1 = 2.85V, VLDO2 = 2.85V per MAX8805_E_EGG+T). Use Value: 35µVRMS noise and 70dB PSRR suppress supply-induced phase noise, preserving EVM and spectral mask compliance. |
| Smartphone Transmitter Architecture | NCDMA Handset Power Management |
Use Scenario: Integrating PA supply, LDO bias, and thermal protection into a single 2mm × 2mm footprint for thin smartphone designs. IC Role / Device Role / Timing Role: Compact, all-in-one power solution replacing discrete buck + dual-LDO + bypass switch combinations. Use Value: Reduces BOM count by ≥7 components and saves >12mm² PCB area versus discrete alternatives. | Use Scenario: Supporting CDMA2000 1xRTT baseband power sequencing where PA voltage must track envelope with sub-µs latency. IC Role / Device Role / Timing Role: High-bandwidth step-down converter with 7.5µs settling time and HP-triggered forced bypass for burst-mode operation. Use Value: Meets NCDMA dynamic range and linearity requirements without requiring external DAC or sequencer logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PA power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX8805WEREGG+T | 2.5V/V REFIN-to-PA gain, 2MHz switching, 650mA output drive | Higher gain enables lower REFIN DAC resolution for same VPA_ range; rated for 50mA higher output current | Select when system DAC has limited voltage range (e.g., 0–0.8V) or PA peak current exceeds 600mA. |
| MAX8805ZEREGG+T | 2V/V REFIN-to-PA gain, 4MHz switching, same 600mA rating | Higher frequency allows smaller inductors and further reduces solution size, but with ~2–3% lower peak efficiency at mid-load | Select when board space is constrained and inductor height <1.0mm is mandatory; verify thermal margin at 4MHz. |
Compared with MAX8805WEREGG+T and MAX8805ZEREGG+T, the MAX8805YEWEGG+T offers optimal balance of gain linearity (2V/V), efficiency (≥92% at 3.6V/300mA), and thermal performance in 2mm × 2mm UCSP-making it preferred for mainstream WCDMA handset designs targeting cost, size, and battery life.
Availability
MAX8805YEWEGG+T is available at Aetrix Electronics and suitable for WCDMA handset production, smartphone RF front-end development, and NCDMA transmitter module manufacturing requiring stable component supply and full RoHS-compliant packaging.
Supply support for MAX8805YEWEGG+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for communications, computing, and consumer markets.
The MAX8805 family was engineered specifically for dynamic PA power delivery in 3G cellular handsets, integrating step-down conversion, bypass FET, and dual LDOs to replace multi-chip solutions while meeting stringent RF noise, efficiency, and footprint requirements.
FAQ
What is the REFIN-to-PA output voltage gain for MAX8805YEWEGG+T?
The MAX8805YEWEGG+T features a fixed 2V/V REFIN-to-PA output voltage gain. When a 0.9V analog voltage is applied to REFIN, the PA output (VPA_) regulates to approximately 1.8V-subject to voltage-positioning correction based on inductor DCR and load current. This gain is confirmed in the Electrical Characteristics table under "REFIN to PA_ Gain" for MAX8805Y/MAX8805Z variants.
Does MAX8805YEWEGG+T support automatic bypass mode, and what triggers it?
Yes, MAX8805YEWEGG+T supports automatic bypass mode triggered when VREFIN exceeds 0.465 × VIN2 (with 50mV hysteresis). This threshold uses VIN2-not VIN1-to avoid false triggering from switching noise. Once engaged, the internal 60mΩ bypass FET connects IN1A/IN1B directly to PAA/PAB, disabling PWM operation and enabling 100% duty-cycle conduction.
What is the maximum continuous output current capability of the PA step-down converter in MAX8805YEWEGG+T?
The MAX8805YEWEGG+T delivers up to 600mA continuous output current in PWM step-down mode. This rating is specified under "Peak Current Limit (p-Channel MOSFET)" as 0.7–1.1A and validated across temperature; actual usable current depends on thermal design, input voltage, and ambient conditions-but 600mA is the guaranteed minimum output under full specification.
Can both LDOs in MAX8805YEWEGG+T be disabled independently?
Yes, the MAX8805YEWEGG+T provides fully independent control of its dual LDOs: EN1 controls LDO1 and EN2 controls LDO2. Each input is active-high and logic-compatible with 2.7–5.5V supplies. When disabled, each LDO output presents 1kΩ shutdown impedance and is internally pulled down via a 1kΩ resistor-ensuring defined voltage states during sleep modes.
What package type and dimensions does MAX8805YEWEGG+T use?
MAX8805YEWEGG+T uses a 16-bump UCSP (Ultra Compact Silicon Package) measuring 2.0mm × 2.0mm × 0.7mm maximum height, with a 4×4 bump grid. This package is lead-free/RoHS-compliant (denoted by '+' in the part number) and requires JEDEC J-STD-020A reflow profile-hand soldering is not permitted due to thermal limitations.
MAX8805YEWEGG+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-WFBGA, WLBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Converter, WCDMA PA Power
- Voltage - Input:
- 2.7V ~ 5.5V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.4V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLP
MAX8805YEWEGG+T FAQ
1.How can I place an order for MAX8805YEWEGG+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8805YEWEGG+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8805YEWEGG+T reliable?
The price and inventory of MAX8805YEWEGG+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8805YEWEGG+T is usually 5 days.
3.What payment methods are accepted for MAX8805YEWEGG+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8805YEWEGG+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8805YEWEGG+T?
MAX8805YEWEGG+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8805YEWEGG+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8805YEWEGG+T?
For technical support, including MAX8805YEWEGG+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8805YEWEGG+T requirements.
6.How does Aetrix verify that MAX8805YEWEGG+T is sourced from the original manufacturer or authorized distributors?
All MAX8805YEWEGG+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8805YEWEGG+T meets industry standards.
7.What is the process for return or replacement of MAX8805YEWEGG+T?
All MAX8805YEWEGG+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX8805YEWEGG+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8805YEWEGG+T part is unused and in its original packaging.
Return procedure for MAX8805YEWEGG+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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