Analog Devices Inc./Maxim Integrated MAX8836ZEREEE+T
- Part No.:
- MAX8836ZEREEE+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WFBGA, CSPBGA
- Datasheet:
-
MAX8836ZEREEE+T.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 16UCSP
- Quantity:
- Payment:

- Shipping:

Inventory:2,322
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Product details
Overview
The MAX8836ZEREEE+T from Maxim Integrated is a 1.2A high-frequency PWM step-down converter with integrated 200mA low-noise LDO, optimized for PA power in WCDMA/CDMA handsets. It delivers fixed 3.1V or 3.4V output via HP pin selection, features 60mΩ bypass FET for ultra-low dropout, ±2% output voltage accuracy, and operates from 2.7V to 5.5V input.
For engineers reviewing the MAX8836ZEREEE+T datasheet, MAX8836ZEREEE+T pinout, MAX8836ZEREEE+T application, or MAX8836ZEREEE+T equivalent, this device supports fast transient response (25µs settling), high PSRR (65dB typ), low LDO noise (35µVRMS typ), and dual independent enable control (PA_EN/EN2) for power sequencing in compact RF front-end designs.
Technical Context
The MAX8836ZEREEE+T integrates two independent regulated power rails: a hysteretic 1.6MHz PWM buck converter driving up to 1.2A into PA loads, and a separate 200mA LDO2 with 2.85V factory-set output. Its voltage-positioning feedback architecture eliminates phase lag from output capacitance, enabling stable operation with only 4.7µF ceramic output caps.
Bypass mode engages automatically above ~99% duty cycle using an internal 60mΩ p-channel FET that connects IN1A/IN1B directly to PAA/PAB, reducing dropout to <100mV at 1A while suppressing switching noise. The LDO2 uses a p-channel pass device with 70mV dropout at 100mA and maintains 65dB PSRR from 10Hz–10kHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | 3.1V or 3.4V selectable via HP pin; enables precise PA bias matching without external resistors. |
| Max Output Current | 1.2A from PWM buck stage; sufficient for high-power RF PA stages in cellular handsets. |
| LDO2 Output | 2.85V fixed, 200mA capable; powers sensitive analog circuitry with low 35µVRMS noise. |
| Bypass FET RDS(ON) | 60mΩ typical; reduces conduction loss and extends battery life during high-duty-cycle transmission. |
| Switching Frequency | 1.6MHz; allows use of small 2.2µH inductors and minimizes EMI filtering requirements. |
| PSRR (LDO2) | 65dB typical (10Hz–10kHz); suppresses supply noise coupling into RF bias paths. |
| Shutdown Current | 0.1µA typical; preserves battery charge during idle/sleep modes in portable devices. |
| Input Voltage Range | 2.7V to 5.5V; compatible with single-cell Li+ batteries and wide-input industrial supplies. |
Pinout & Package
MAX8836ZEREEE+T is housed in a 16-bump, 2mm × 2mm × 0.7mm UCSP package (R162A2+1), optimized for space-constrained mobile PCBs with fine-pitch bump layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 (REFBP) | Reference noise bypass | Internal bandgap reference node; requires 0.22µF ceramic cap to AGND to reduce LDO output noise. |
| A2 (AGND) | Analog ground | Low-noise reference plane for LDO and reference circuits; must be tied to PGND via common ground plane. |
| A3 (N.I.C.) | Not internally connected | Thermal pad; connect to AGND to improve heat dissipation in high-power operation. |
| A4 (PGND) | Power ground | Return path for buck converter switching current; separate from AGND but joined on PCB for noise isolation. |
| B1 (LDO2) | LDO2 output | 200mA regulated 2.85V supply; requires 1µF ceramic cap near pin for stability and transient response. |
| B2 (PA_EN) | PA buck enable | Active-high logic control; internal 800kΩ pulldown ensures safe default-off state at power-up. |
| B3 (EN2) | LDO2 enable | Independent active-high enable; allows sequenced power-up of PA and auxiliary analog rails. |
| B4 (LX) | Inductor switch node | High-current connection to external 2.2µH inductor; critical for EMI control-keep trace short and wide. |
| C1 (IN2) | LDO2 & reference supply | Input for LDO2 and internal reference; must match IN1A/IN1B source to prevent false bypass activation. |
| C2 (HP) | Output voltage select | Logic-selectable 3.1V (HP=1) or 3.4V (HP=0); internal 800kΩ pulldown sets default to 3.4V. |
| C3/C4 (IN1B/IN1A) | PA buck input | Parallel-connected 2.7V–5.5V inputs; require 4.7µF ceramic bypass caps each to PGND for low-impedance sourcing. |
| D1 (N.C.) | No connect | Internally tied to IN2; leave unconnected or tie to AGND-no functional role in circuit operation. |
| D2 (T.P.) | Factory test point | Internal 120kΩ pulldown to AGND; must be left floating or grounded-no user signal connection. |
| D3/D4 (PAB/PAA) | PA output (bypass mode) | Direct connection to IN1A/IN1B during bypass; require 4.7µF ceramic caps to PGND for ripple suppression. |
Key Features
| Feature | Design Value |
|---|---|
| Hysteretic PWM control | Enables 1.6MHz switching with zero current overshoot, eliminating need for external compensation and supporting 2.2µH inductors. |
| Voltage-positioning feedback | Removes output capacitor phase lag from control loop, allowing stable regulation with minimal 4.7µF ceramic output capacitance. |
| Auto-bypass mode | Engages above ~99% duty cycle using internal 60mΩ FET-reduces dropout to <100mV at 1A and eliminates switching noise in PA bias path. |
| Independent dual enable | Separate PA_EN and EN2 pins allow precise sequencing of RF PA and LDO-powered analog blocks during startup/shutdown. |
| Ultra-low LDO noise | 35µVRMS (100Hz–100kHz) output noise and 65dB PSRR ensure clean bias for low-phase-noise VCOs and sensitive RF receivers. |
| Thermal shutdown protection | Activates at +160°C junction temperature with 20°C hysteresis, preventing damage during sustained overload or poor heatsinking. |
Applications
| WCDMA/CDMA Handset PA Power | Smartphone RF Front-End Bias |
|---|---|
|
Use Scenario: Delivering stable 3.4V bias to power amplifier during high-duty-cycle transmission bursts in 3G handsets. IC Role / Device Role / Timing Role: Dual-rail PMIC providing switched-mode efficiency for PA drive and low-noise LDO for bias control. Use Value: Bypass mode cuts dropout to <100mV at 1A, extending talk time by minimizing battery voltage sag under peak load. |
Use Scenario: Supplying sequenced 3.1V/3.4V PA voltage and 2.85V LDO rail to RF transceiver ICs in multi-band smartphones. IC Role / Device Role / Timing Role: Integrated buck+LDO power solution with independent enables for controlled power-up of RF subsystems. Use Value: 25µs output voltage settling between 3.1V↔3.4V supports rapid PA mode switching in adaptive envelope tracking architectures. |
| Wireless PDA Baseband Power | Portable RF Test Equipment |
|
Use Scenario: Generating clean 2.85V supply for baseband processor analog peripherals (ADCs, DACs, PLLs) in handheld PDAs. IC Role / Device Role / Timing Role: Low-noise LDO2 regulator decoupling digital noise from sensitive analog signal chains. Use Value: 65dB PSRR and 35µVRMS noise prevent digital switching artifacts from degrading SNR in audio/RF sampling circuits. |
Use Scenario: Providing regulated, low-ripple DC bias to lab-grade RF power amplifiers and signal generators in portable test gear. IC Role / Device Role / Timing Role: Compact, high-efficiency dual-output DC-DC converter enabling battery-operated precision instrumentation. Use Value: 2mm × 2mm UCSP footprint and 0.1µA shutdown current support >100-hour battery runtime in field-deployable test tools. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-rail PA power applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX8835ZEREEE+T | Same 16-bump UCSP package and pinout; lacks LDO2-only provides 1.2A buck output with 3.1V/3.4V selection. | Suitable where only PA rail is needed; cannot replace MAX8836ZEREEE+T when 2.85V LDO2 is required for analog bias. | Select MAX8835ZEREEE+T if system uses separate LDO for analog rails; verify absence of LDO2 does not impact noise-sensitive functions. |
| TPS62260DRVR | Single 1.2A buck converter (no integrated LDO); 3MHz switching, 2.05–6.5V input, adjustable output via resistor divider. | Requires external components for voltage setting and noise filtering; no auto-bypass or HP-selectable fixed outputs. | Choose TPS62260DRVR only when design flexibility (adjustable VOUT) outweighs need for integrated LDO2 and fixed 3.1V/3.4V PA bias. |
Compared with MAX8836ZEREEE+T, MAX8835ZEREEE+T offers identical PA buck functionality but omits the 200mA LDO2 rail, while TPS62260DRVR provides higher switching frequency and input range but demands external configuration and lacks integrated bypass/LDO features critical for cellular PA applications.
Availability
MAX8836ZEREEE+T is available at Aetrix Electronics and suitable for WCDMA handset design, smartphone RF front-end development, and portable wireless test equipment requiring stable component supply with full lifecycle support.
Supply support for MAX8836ZEREEE+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for demanding applications in communications, computing, and industrial systems.
The MAX8836ZEREEE+T belongs to Maxim's high-efficiency, ultra-compact PMIC family targeting RF power amplifier bias in battery-powered cellular devices, emphasizing low dropout, low noise, and automatic mode switching.
FAQ
What output voltages does the MAX8836ZEREEE+T support?
The MAX8836ZEREEE+T provides two fixed PA output voltages: 3.4V when HP = 0 (grounded), and 3.1V when HP = 1 (high). Its LDO2 output is factory-set to 2.85V and cannot be adjusted. Both outputs are internally trimmed to ±2% accuracy across temperature and load conditions, eliminating need for external feedback resistors in standard implementations.
How does bypass mode operate in the MAX8836ZEREEE+T?
Bypass mode in the MAX8836ZEREEE+T activates automatically when the PWM buck operates above ~99% duty cycle, connecting IN1A/IN1B directly to PAA/PAB through an internal 60mΩ p-channel FET. This reduces dropout to under 100mV at 1A load, eliminates switching noise on the PA rail, and improves efficiency during high-power transmission bursts-critical for WCDMA/CDMA handset battery life.
Can the MAX8836ZEREEE+T be used without the LDO2 function?
Yes-the LDO2 function in the MAX8836ZEREEE+T is independently disabled via the EN2 pin. When EN2 is held low, LDO2 shuts down and its output is pulled to ground through a 1kΩ internal resistor. The PA buck converter remains fully operational with PA_EN high, making MAX8836ZEREEE+T usable in designs requiring only the 3.1V/3.4V PA rail.
What is the recommended inductor for the MAX8836ZEREEE+T PA buck stage?
The MAX8836ZEREEE+T is optimized for a 2.2µH shielded inductor such as the FDK MIPF2520 series, rated for ≥1.2A DC current with 50–150mΩ DCR. This value supports stable 1.6MHz operation, minimizes size, and ensures fast transient response. Inductors with higher DCR increase dropout; lower values risk peak current limit triggering and reduced efficiency at light loads.
Does the MAX8836ZEREEE+T require external compensation components?
No-the MAX8836ZEREEE+T uses a hysteretic PWM control scheme with voltage-positioning feedback, which eliminates the need for external compensation networks. Its internal loop is inherently stable with the recommended 4.7µF ceramic output capacitor, simplifying design and reducing bill-of-materials cost compared to traditional voltage-mode buck controllers.
MAX8836ZEREEE+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-WFBGA, CSPBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 1.6MHz
- Voltage/Current - Output 1:
- 3.1V/3.4V, 1.2A
- Voltage/Current - Output 2:
- 2.85V, 200mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-UCSP (2.08x2.08)
MAX8836ZEREEE+T FAQ
1.How can I place an order for MAX8836ZEREEE+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX8836ZEREEE+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX8836ZEREEE+T reliable?
The price and inventory of MAX8836ZEREEE+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX8836ZEREEE+T is usually 5 days.
3.What payment methods are accepted for MAX8836ZEREEE+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX8836ZEREEE+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX8836ZEREEE+T?
MAX8836ZEREEE+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX8836ZEREEE+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX8836ZEREEE+T?
For technical support, including MAX8836ZEREEE+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX8836ZEREEE+T requirements.
6.How does Aetrix verify that MAX8836ZEREEE+T is sourced from the original manufacturer or authorized distributors?
All MAX8836ZEREEE+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX8836ZEREEE+T meets industry standards.
7.What is the process for return or replacement of MAX8836ZEREEE+T?
All MAX8836ZEREEE+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX8836ZEREEE+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX8836ZEREEE+T part is unused and in its original packaging.
Return procedure for MAX8836ZEREEE+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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