Analog Devices Inc./Maxim Integrated MAX9152ESE+

Overview

The MAX9152ESE+ from Maxim Integrated is a 2×2 LVDS/LVPECL-to-LVDS crosspoint switch IC designed for high-speed signal routing in timing-critical interconnects. It supports 800Mbps data rates, delivers ultra-low 120ps_Pk-Pk (max) PRBS jitter, and features pin-programmable configurations including 2:1 mux, 1:2 demux, splitter, and dual repeater modes. It operates from a single +3.3V supply across –40°C to +85°C and targets fault-tolerant telecom infrastructure.

For engineers reviewing the MAX9152ESE+ datasheet, MAX9152ESE+ pinout, MAX9152ESE+ application, or MAX9152ESE+ equivalent, key selection criteria include differential channel skew (<50ps), selectable 75Ω/100Ω output impedance, LVPECL input compatibility without level-shifting, and SO-16 package compatibility with DS90CP22 upgrades.

Technical Context

The MAX9152ESE+ implements a fully differential analog switch matrix with two LVDS/LVPECL inputs and two LVDS outputs, controlled by LVCMOS/LVTTL logic pins (SEL0/SEL1, EN0/EN1). Its internal architecture enables dynamic reconfiguration between four distinct signal-path topologies without external components.

It integrates programmable differential output resistance (60–155Ω) via NC/RSEL pin, supports fail-safe biasing via external resistors, and maintains sub-50ps channel-to-channel skew across all operating modes. AC performance is characterized using PRBS23 patterns at 800Mbps with 200mV differential input swing and 1.2V common-mode voltage.

Key Specifications

Pinout & Package

The MAX9152ESE+ is housed in a 16-pin SO (Small Outline) package with standard 1.27mm pitch, compatible with JEDEC MS-012AC. Pin 9 is NC; VCC (Pin 5) and GND (Pin 12) require local 0.1µF + 0.001µF ceramic bypassing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed differential crosspoint applications.

Compared with DS90CP22MTDX/NOPB and MAX9154ESE+, the MAX9152ESE+ uniquely balances ultra-low jitter (≤120ps), LVPECL input compatibility, and minimal 109mW power in a space-constrained SO-16 footprint - making it the preferred choice for new 2×2 LVDS signal routing in telecom timing subsystems.

Availability

The MAX9152ESE+ is available at Aetrix Electronics and suitable for cell phone base stations, digital crossconnects, and cable repeater systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for production ramp.

Supply support for MAX9152ESE+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, communications, and computing markets.

The MAX9152ESE+ belongs to Maxim's high-speed interface product line, engineered specifically for low-jitter, low-power LVDS signal routing in telecom infrastructure and datacom equipment where signal integrity and configurability are critical.

FAQ

What is the maximum data rate supported by the MAX9152ESE+?

The MAX9152ESE+ supports a guaranteed maximum data rate of 800Mbps under specified conditions (PRBS23 pattern, 200mV differential input, 1.2V common-mode voltage). This rating is validated across the full –40°C to +85°C temperature range and with 3.0V–3.6V supply voltage. The MAX9152ESE+ maintains compliance with ANSI TIA/EIA-644 LVDS specifications at this rate, enabling use in SONET OC-12 and Gigabit Ethernet physical layer interfaces.

Does the MAX9152ESE+ support LVPECL inputs without external level shifting?

Yes, the MAX9152ESE+ accepts LVPECL signals directly at its IN0± and IN1± inputs without external level-shifting circuitry. Its differential input stage is designed to operate with LVPECL common-mode voltages (typically ~2.0V), and the datasheet confirms compatibility with both LVDS and LVPECL signaling standards. For standard PECL (5V), an external attenuation network (e.g., Figure 9 in the datasheet) is required before connecting to the MAX9152ESE+.

How does the NC/RSEL pin affect output performance in the MAX9152ESE+?

The NC/RSEL pin on the MAX9152ESE+ selects the differential output impedance: open or low configures 75Ω output resistance, while high configures 100Ω. This setting directly impacts signal integrity on transmission lines - matching the output impedance to the characteristic impedance of the PCB trace or cable minimizes reflections and improves eye diagram quality. The MAX9152ESE+ specifies corresponding VOD (280–470mV) and RDIFF (60–155Ω) values for each mode.

Can the MAX9152ESE+ be used in a 1:2 splitter configuration, and how is it enabled?

Yes, the MAX9152ESE+ supports 1:2 splitting, where one input drives both outputs simultaneously. This mode is enabled by setting SEL0 = SEL1 = low (L/L), as defined in Table 1 of the datasheet. In this configuration, the MAX9152ESE+ repeats the selected input signal identically on both OUT0 and OUT1, preserving amplitude and timing alignment with ≤50ps channel skew - ideal for clock fanout or redundant signal distribution.

What is the power dissipation of the MAX9152ESE+ under typical operating conditions?

The MAX9152ESE+ dissipates 109mW total under typical quiescent conditions (enabled, no switching) at +3.3V and +25°C. At full 800Mbps switching, supply current rises to 52–70mA depending on load (75Ω vs. 100Ω) and configuration, resulting in ~170–230mW total power consumption. Thermal design should account for the SO-16 package's 8.7mW/°C derating above +70°C ambient, with maximum junction temperature rated at +150°C.