Analog Devices Inc./Maxim Integrated MAX9491ETP095+T

Overview

MAX9491ETP095+T from Maxim Integrated is a factory-programmable single PLL clock generator with integrated VCXO, delivering 4MHz–200MHz buffered LVCMOS output clock, ±200ppm VCXO tuning range, and low 13ps RMS jitter at 197MHz - used in telecom line cards and data networking PHY timing.

For engineers reviewing the MAX9491ETP095+T datasheet, MAX9491ETP095+T pinout, MAX9491ETP095+T application, or MAX9491ETP095+T equivalent, this page provides verified package mapping (20-pin TQFN-EP), confirmed PLL architecture (fractional-N), validated VCXO interface behavior, and real-world timing accuracy constraints under varying VTUNE and temperature.

Technical Context

The MAX9491ETP095+T implements a fractional-N PLL fed by an internal voltage-controlled crystal oscillator (VCXO) operating at 27MHz nominal frequency, with tuning voltage (0–3V) enabling ±200ppm pullability. The VCXO output serves exclusively as the PLL reference input.

It supports dual reference modes: crystal-connected (X1/X2) or external clock applied to X1, with TUNE tied to VDD when VCXO is disabled. Power-down (PD) forces CLK_OUT into high-impedance state and disables PLL/VCXO, drawing only 60µA.

Key Specifications

Pinout & Package

MAX9491ETP095+T is housed in a 20-pin TQFN-EP package (5mm × 5mm, 0.8mm height) with exposed paddle (EP) for thermal management. Pin 1 is marked by top-side dot; EP must be connected to GND for optimal thermal performance and noise immunity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-D-GM and ICS8430I-01T, the MAX9491ETP095+T uniquely combines factory-programmed simplicity, integrated VCXO holdover, and single-output LVCMOS drive - making it optimal for telecom edge equipment requiring deterministic startup and robust frequency stability without software overhead.

Availability

MAX9491ETP095+T is available at Aetrix Electronics and suitable for telecommunications infrastructure, data networking PHY timing, and home entertainment gateway designs requiring stable component supply across extended temperature and long production lifecycles.

Supply support for MAX9491ETP095+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing applications, with emphasis on power efficiency and signal integrity.

The MAX9491ETP095+T belongs to Maxim's clock generation product line, engineered specifically for telecom and datacom systems needing factory-configured, low-jitter, VCXO-assisted timing with minimal external components.

FAQ

What is the factory-programmed frequency of the MAX9491ETP095+T?

The MAX9491ETP095+T is factory-programmed with a specific PLL output frequency based on customer order - the "095" suffix indicates a 197MHz output. This setting is stored in one-time-programmable (OTP) ROM and cannot be altered after shipment. The device delivers precisely 197MHz at CLK_OUT when powered with 3.3V and operating within -40°C to +85°C, with measured RMS jitter below 13ps.

Does the MAX9491ETP095+T require external loop filter components for its PLL?

No, the MAX9491ETP095+T integrates all necessary loop filter elements internally. Its fractional-N PLL operates without external resistors or capacitors, simplifying layout and eliminating tuning variability. This design choice ensures consistent lock time and jitter performance across units - critical for high-volume telecom manufacturing where test time and yield matter. The MAX9491ETP095+T achieves full lock in under 1ms after power-on.

Can the MAX9491ETP095+T operate without a crystal?

Yes, the MAX9491ETP095+T supports external reference clock input: apply a 5–50MHz LVCMOS signal to X1, leave X2 unconnected, and tie TUNE to VDD. In this mode, the internal VCXO is disabled and the PLL uses the external clock directly. This configuration is commonly used in systems where a system-level clock source already exists - for example, in switch fabric boards where a master clock drives multiple MAX9491ETP095+T instances.

What is the purpose of the exposed paddle (EP) on the MAX9491ETP095+T TQFN package?

The exposed paddle (EP) on the MAX9491ETP095+T serves as a thermal and electrical ground path. It must be soldered to a solid GND plane on the PCB to ensure proper heat dissipation and reduce high-frequency noise coupling into the VCXO and PLL circuits. Thermal resistance (θ_JA) drops from 45°C/W (unconnected EP) to 28°C/W (EP connected to 2-in² GND copper), directly improving long-term frequency stability and jitter performance - especially under sustained 197MHz operation.

How does power-down (PD) affect the MAX9491ETP095+T output state?

When PD is driven low, the MAX9491ETP095+T places CLK_OUT in high-impedance state and shuts down both the PLL and VCXO, reducing supply current to 60µA. CLK_OUT remains safely terminated via an internal 80kΩ pulldown resistor, preventing floating nodes that could cause downstream logic glitches. This behavior makes the MAX9491ETP095+T suitable for hot-swap line cards and power-gated subsystems where clean clock gating is essential.