Analog Devices Inc./Maxim Integrated MAX9601EUP+

Overview

MAX9601EUP+ from Maxim Integrated is a dual-channel ultra-high-speed PECL-output comparator with 500ps propagation delay, 10ps channel skew, and 30ps propagation delay dispersion. It features latch-enable (LE_, LE_) and adjustable current-controlled hysteresis (HYS_), operates from -5.2V/+5V supplies, and drives 50Ω transmission lines directly-ideal for high-fidelity pulse tracking in VLSI ATE and scope front ends.

For engineers reviewing the MAX9601EUP+ datasheet, MAX9601EUP+ pinout, MAX9601EUP+ application, or MAX9601EUP+ equivalent, this page delivers verified technical context, real-world timing behavior, PECL output interface constraints, latch timing requirements (tLS = 250ps, tLH = 300ps), and validated alternatives for high-speed signal conditioning designs.

Technical Context

The MAX9601EUP+ implements a bipolar differential input stage with common-mode range from (VEE + 3V) to (VCC − 2V), supporting −2.2V to +3V input swing under ±5.2V/5V supplies. Its open-emitter PECL outputs require external 50Ω pull-downs to VT = VCCO_ − 2V and sink current into termination-no internal level-shifting or active drivers.

Latch operation follows a differential truth table: LE_ low / LE_ high enables compare mode; LE_ high / LE_ low triggers latching. Hysteresis is set by RHYS_ (10kΩ–35kΩ to GND), yielding 5mV–60mV input-referred hysteresis, with zero hysteresis achieved by leaving HYS_ open or tied to VCC.

Key Specifications

Pinout & Package

MAX9601EUP+ is housed in a 20-pin TSSOP package (4.4mm body width) with exposed pad for thermal enhancement. Pin 1 is QA (Channel A output), pin 2 is QA (Channel A complementary output), pins 6 and 15 are VEE, pins 7 and 14 are VCC, and pins 18 and 3 are dedicated to VCCOA and GND respectively for independent output driver biasing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-high-speed comparator applications.

Compared with MAX9601EUP+, MAX9600EUP+ offers identical functionality but ECL-level outputs requiring different termination, while ADCMP572BCPZ-R7 trades dual-channel correlation and latch control for lower single-channel delay and LVDS compatibility-making it unsuitable for track-hold or multi-signal alignment tasks.

Availability

MAX9601EUP+ is available at Aetrix Electronics and suitable for VLSI ATE, high-speed instrumentation, oscilloscope front ends, and signal restoration systems requiring stable component supply, guaranteed -40°C to +85°C operation, and production-ready TSSOP packaging.

Supply support for MAX9601EUP+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for demanding timing, signal integrity, and power efficiency applications.

The MAX9600/MAX9601/MAX9602 family was designed specifically for ultra-high-speed test and measurement systems where sub-nanosecond timing fidelity, channel-to-channel matching, and noise-immune decision thresholds are mandatory-targeting ATE, oscilloscopes, and high-speed communications infrastructure.

FAQ

What is the correct termination scheme for MAX9601EUP+ PECL outputs?

The MAX9601EUP+ PECL outputs require external 50Ω pull-down resistors connected from QA/QA and QB/QB to VT = VCCO_ − 2V. This ensures valid VOH and VOL levels per PECL specification. Using 50Ω to GND (as with MAX9600EUP+) results in invalid logic states. VCCO_ must be supplied separately and matches the target PECL system's logic reference voltage.

Does MAX9601EUP+ support true differential latch-enable signaling?

Yes, MAX9601EUP+ uses fully differential latch-enable inputs (LEA/LEA and LEB/LEB). The device enters compare mode when LE_ is low and LE_ is high, and latches when LE_ is high and LE_ is low. Invalid states (both high or both low) place outputs in unknown logic states. This differential architecture rejects common-mode noise on the latch control path.

How is hysteresis configured on MAX9601EUP+ and what range does it support?

Hysteresis on MAX9601EUP+ is set by connecting a single resistor (RHYS_) from HYSA or HYSB to GND. Values from 10kΩ to 35kΩ yield input-referred hysteresis from 60mV down to 5mV. Leaving HYS_ open or tying it to VCC disables hysteresis entirely. This current-controlled method avoids external voltage references and simplifies layout.

What is the maximum input slew rate requirement to avoid oscillation in MAX9601EUP+?

To prevent oscillation during threshold crossing, MAX9601EUP+ requires ≥5V/µs input slew rate under typical conditions. Slower slew rates increase susceptibility to parasitic feedback; adding hysteresis (via RHYS_) mitigates this. Layout quality and source impedance also affect the effective minimum slew rate-poor grounding or long traces raise the required minimum.

Can MAX9601EUP+ operate with non-standard supply voltages like +6V/−4.2V?

Yes, MAX9601EUP+ supports supply ranges beyond ±5.2V/5V: VCC = 4.3V to 6.3V and VEE = −6V to −4V are fully specified. With +6V/−4.2V supplies, the input common-mode range extends to −1.2V to +4V, and output swing remains compliant when VCCO_ is set appropriately-enabling interoperability with mixed-voltage PECL systems.