Analog Devices Inc./Maxim Integrated MAX96717FGTJ/VY+T
- Part No.:
- MAX96717FGTJ/VY+T
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Serializers, Deserializers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
MAX96717FGTJ/VY+T.pdf
- Description:
- TUNNELING, 3GB/S ONLY CSI-2 TO G
- Quantity:
- Payment:

- Shipping:

Inventory:1,358
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Product details
Overview
MAX96717FGTJ/VY+T from Analog Devices is a GMSL2 serializer that converts MIPI CSI-2 video input (up to 4-lane D-PHY v1.2, 2.5Gbps/lane) into a 3Gbps forward / 187.5Mbps reverse full-duplex GMSL2 serial link over coax or STP cables. It supports ASIL-B functional safety, includes dual I2C/UART pass-through channels, SPI tunneling, integrated ADC and temperature sensor, and operates across -40°C to +105°C for automotive ADAS camera systems.
For engineers reviewing the MAX96717FGTJ/VY+T datasheet, MAX96717FGTJ/VY+T pinout, MAX96717FGTJ/VY+T application, or MAX96717FGTJ/VY+T equivalent, key selection criteria include GMSL2 link rate compatibility, MIPI CSI-2 virtual channel support (16 VC), RoR clocking for crystal-free operation, side-channel peripheral interfacing capability, and AEC-Q100 Grade 2 qualification for automotive deployment.
Technical Context
The MAX96717FGTJ/VY+T implements a deterministic GMSL2 packet protocol with 9b10b encoding, R-S FEC for forward video/control data, and CRC protection for side-channel and video payloads. Its adaptive equalization (AEQ) and echo cancellation dynamically compensate for cable loss up to -19.5dB at 1.5GHz, enabling reliable 20m transmission over aged 50Ω foam-dielectric coax at +105°C.
It integrates a scheduler/arbiter for bandwidth sharing between pixel-mode video streams and tunneling-mode side-channel traffic, supports polarity flip and lane reassignment on MIPI input, and provides reference-over-reverse (RoR) clocking to eliminate external crystal requirements for image sensors - all while maintaining end-to-end data integrity via ECC, checksums, and local/remote error flagging.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| GMSL2 Forward Rate | 3Gbps fixed - enables uncompressed 4Mp@40fps video transport over single coax/STP without compression artifacts. |
| GMSL2 Reverse Rate | 187.5Mbps fixed - supports real-time bidirectional control, configuration, and diagnostics across the same physical link. |
| MIPI CSI-2 Input | 4-lane D-PHY v1.2, 2.5Gbps/lane - compatible with high-resolution automotive image sensors including C-PHY v1.0 via adapter mode. |
| Virtual Channels | 16 - allows concurrent multiplexing of multiple camera streams or sensor data types within one GMSL2 link. |
| Operating Temp | -40°C to +105°C - meets automotive ambient requirements for front-camera, surround-view, and driver-monitor mounting locations. |
| AEC-Q100 Grade | Grade 2 - qualified for under-hood and cabin-mounted ADAS ECUs per automotive reliability standards. |
| Functional Safety | ASIL-B compliant - achieves required fault coverage via CRC, R-S FEC, ECC, and comprehensive diagnostic registers. |
Pinout & Package
MAX96717FGTJ/VY+T is housed in a compact 5mm × 5mm TQFN-SW (Side-Wettable) package with 0.5mm pitch and 32 pins, optimized for automated optical inspection (AOI) and automotive thermal cycling reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | MIPI CSI-2 Data Lanes | High-speed differential inputs accepting D-PHY HS/LP signals; support polarity flip and lane reassignment. |
| CLKIN | MIPI Clock Lane Input | Accepts D-PHY clock signal up to 1.5GHz; enables synchronization of multi-lane video capture. |
| GMSL+ / GMSL− | GMSL2 Differential Pair | Full-duplex AC-coupled interface supporting 3Gbps forward + 187.5Mbps reverse data over coax or STP. |
| SIOA–SIOD | I2C/UART Side-Channel Pins | Four dedicated pins for main I2C/UART interface; configurable as open-drain or push-pull with CRC/message counter support. |
| GPIO0–GPIO3 | Programmable GPIO | Register-configurable digital I/O supporting interrupt generation, sync signaling, or status indication. |
Key Features
| Feature | Design Value |
|---|---|
| Reference Over Reverse (RoR) | Generates precise image sensor reference clock from reverse-link timing - eliminates need for external crystal and reduces BOM cost/PCB area. |
| Integrated ADC | 10-bit SAR ADC with internal/external voltage monitoring and round-robin sampling - enables real-time supply and die temperature supervision without external components. |
| Eye-Opening Monitor | On-chip real-time link quality metric derived from equalizer tap coefficients - provides actionable feedback for cable health and EOL margin assessment. |
| SPI Tunneling | Transparent SPI master/subordinate passthrough over GMSL2 link - allows host SoC to directly configure peripherals (e.g., ISP, PMIC) located at camera module. |
| Delay-Compensated Mode | Hardware-based skew compensation across MIPI lanes and GMSL2 link - ensures deterministic latency for time-synchronized multi-camera systems. |
Applications
| Advanced Driver Assistance Systems (ADAS) | Rear-View Camera (RVC) |
|---|---|
Use Scenario: Front-facing 4Mp@40fps camera feeding object detection and lane departure algorithms in autonomous emergency braking systems. IC Role / Device Role / Timing Role: MIPI-to-GMSL2 serializer providing low-latency, ASIL-B-compliant video transport with RoR clocking for sensor synchronization. Use Value: Enables crystal-free, high-fidelity video transmission over 20m coax while meeting ISO 26262 diagnostic coverage targets. | Use Scenario: Compact rear-view camera module mounted on vehicle tailgate, requiring robust EMI immunity and long-cable reach. IC Role / Device Role / Timing Role: Serializer handling MIPI CSI-2 video and bidirectional I2C control over single coax with PoC support. Use Value: Reduces wiring harness complexity by consolidating power, video, and control onto one shielded cable - simplifying mechanical integration and lowering weight. |
| Surround View Systems (SVS) | Driver Monitor Systems (DMS) |
Use Scenario: Four synchronized camera modules (front, rear, left/right) feeding stitched 360° view to infotainment display. IC Role / Device Role / Timing Role: GMSL2 serializer with frame-sync and delay-compensated mode ensuring sub-microsecond inter-camera timing alignment. Use Value: Eliminates visible stitching artifacts by guaranteeing deterministic end-to-end latency across all four links. | Use Scenario: In-cabin IR camera capturing driver eye/gaze behavior, requiring low-noise analog sensing and secure side-channel communication. IC Role / Device Role / Timing Role: Serializer with integrated ADC and I2C/UART pass-through for direct connection to IR LED drivers and ambient light sensors. Use Value: Integrates power monitoring, temperature sensing, and peripheral control in one device - reducing component count and improving system-level functional safety compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar GMSL2 serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX96712GTJ/VY+T | Lower forward rate (1.5Gbps), no RoR clocking, 12-pin TQFN, no integrated ADC | Targeted for 1080p@30fps SVS or RVC where bandwidth and crystal-free operation are not required | Select when cost sensitivity outweighs need for 4Mp support or ASIL-B diagnostics |
| DS90UB953TRGCRQ1 | FPD-Link III serializer (not GMSL2), 3.12Gbps forward, no built-in ADC, different register map and side-channel architecture | Used in legacy TI-based ADAS platforms; requires separate clock source and lacks RoR capability | Choose only for FPD-Link III ecosystem compatibility - not drop-in replacement for GMSL2 infrastructure |
Compared with MAX96712GTJ/VY+T and DS90UB953TRGCRQ1, the MAX96717FGTJ/VY+T delivers higher bandwidth, integrated functional safety features, and RoR clocking - making it uniquely suited for next-generation 4Mp ADAS cameras requiring single-cable simplicity and ASIL-B compliance.
Availability
MAX96717FGTJ/VY+T is available at Aetrix Electronics and suitable for Advanced Driver Assistance Systems (ADAS), Surround View Systems (SVS), and Driver Monitor Systems (DMS) requiring stable component supply, automotive-grade lifecycle management, and traceable sourcing.
Supply support for MAX96717FGTJ/VY+T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technologies, serving automotive, industrial, communications, and consumer markets with precision ICs and system solutions.
The MAX96717FGTJ/VY+T belongs to Analog Devices' GMSL2 serializer product line, engineered specifically for high-bandwidth, safety-critical automotive camera links - emphasizing deterministic latency, ASIL-B compliance, and single-cable integration of power, video, and control.
FAQ
What is the maximum supported cable length for MAX96717FGTJ/VY+T over coax at +105°C?
The MAX96717FGTJ/VY+T supports up to 20m over 3.2mm Ø 50Ω foam-dielectric coax at +105°C, based on its -19.5dB insertion loss budget at 1.5GHz and adaptive equalization. This assumes aged cable conditions and worst-case attenuation of 1.1dB/m. For solid-dielectric coax or STP, maximum lengths reduce to 10m and 11m respectively under identical thermal conditions.
Does MAX96717FGTJ/VY+T support crystal-free operation for image sensors?
Yes, the MAX96717FGTJ/VY+T supports Reference Over Reverse (RoR) clocking, generating a precise, low-jitter reference clock for the image sensor directly from the GMSL2 reverse-link timing. This eliminates the need for an external crystal oscillator at the camera module, reducing BOM cost, PCB area, and potential failure points in harsh automotive environments.
How many virtual channels does MAX96717FGTJ/VY+T support on its MIPI CSI-2 interface?
The MAX96717FGTJ/VY+T supports 16 virtual channels on its MIPI CSI-2 input interface. This enables concurrent multiplexing of multiple video streams (e.g., RGB, depth, IR) or sensor data types within a single GMSL2 link - essential for multi-function camera modules used in ADAS and DMS applications.
What functional safety certifications apply to MAX96717FGTJ/VY+T?
The MAX96717FGTJ/VY+T is AEC-Q100 Grade 2 qualified and ASIL-B compliant per ISO 26262. Its functional safety features include end-to-end CRC protection, Reed-Solomon FEC for forward data, ECC and checksum-based error detection, and a comprehensive diagnostic register set - all validated for use in automotive safety-related systems.
Can MAX96717FGTJ/VY+T interface with peripherals via SPI tunneling?
Yes, the MAX96717FGTJ/VY+T provides transparent SPI tunneling functionality, allowing the host SoC to communicate directly with peripherals (e.g., ISP, PMIC, or LED drivers) located at the remote camera module over the GMSL2 link. This is implemented as a hardware-accelerated passthrough mode with configurable clock polarity and phase, preserving full SPI timing fidelity.
MAX96717FGTJ/VY+T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Serializer
- Data Rate:
- 3Gbps
- Input Type:
- CML
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- 1
- Number of Outputs:
- 1
- Voltage - Supply:
- 0.95V ~ 1.26V, 1.7V ~ 1.9V, 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-TQFN-EP (5x5)
MAX96717FGTJ/VY+T FAQ
1.How can I place an order for MAX96717FGTJ/VY+T through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX96717FGTJ/VY+T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX96717FGTJ/VY+T reliable?
The price and inventory of MAX96717FGTJ/VY+T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX96717FGTJ/VY+T is usually 5 days.
3.What payment methods are accepted for MAX96717FGTJ/VY+T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX96717FGTJ/VY+T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX96717FGTJ/VY+T?
MAX96717FGTJ/VY+T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX96717FGTJ/VY+T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX96717FGTJ/VY+T?
For technical support, including MAX96717FGTJ/VY+T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX96717FGTJ/VY+T requirements.
6.How does Aetrix verify that MAX96717FGTJ/VY+T is sourced from the original manufacturer or authorized distributors?
All MAX96717FGTJ/VY+T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX96717FGTJ/VY+T meets industry standards.
7.What is the process for return or replacement of MAX96717FGTJ/VY+T?
All MAX96717FGTJ/VY+T units undergo pre-shipment inspection (PSI). If there is an issue with MAX96717FGTJ/VY+T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX96717FGTJ/VY+T part is unused and in its original packaging.
Return procedure for MAX96717FGTJ/VY+T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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