Analog Devices Inc./Maxim Integrated MAX96724FGTN/VY+
- Part No.:
- MAX96724FGTN/VY+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Serializers, Deserializers
- Package:
- 56-WFQFN Exposed Pad
- Datasheet:
-
MAX96724FGTN/VY+.pdf
- Description:
- GMSL2/1 TUNNELING QUAD DESERIALI
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
The MAX96724FGTN/VY+ from Analog Devices is a quad-input GMSL2/1-to-MIPI CSI-2 deserializer for automotive camera links, supporting 3Gbps/6Gbps forward and 187.5Mbps reverse data rates over coax or STP, with MIPI D-PHY v1.2 (2.5Gbps/lane) and C-PHY v1.0 (5.7Gbps/lane) outputs, ASIL-B compliance, and operation from −40°C to +105°C - deployed in high-resolution ADAS camera modules.
For engineers reviewing the MAX96724FGTN/VY+ datasheet, MAX96724FGTN/VY+ pinout, MAX96724FGTN/VY+ application, or MAX96724FGTN/VY+ equivalent, key selection criteria include GMSL2 tunneling capability, MIPI output lane configuration (2×4 or 4×2), RoR clocking support, GPIO/I²C reverse-channel resources, and TQFN-SW 56-pin package compatibility with automotive PCB layout constraints.
Technical Context
The MAX96724FGTN/VY+ implements a quad-channel GMSL2/1 deserialization architecture with independent link-rate configuration per input (6/3Gbps forward, 187.5Mbps reverse), enabling mixed-mode pixel/tunnel operation across coax or STP interconnects. It integrates dual MIPI CSI-2 v1.3 outputs supporting both D-PHY and C-PHY physical layers with aggregation/replication logic and virtual channel mapping (16/32 VC).
Its reverse channel provides bidirectional control via two I²C ports (≤1Mbps), nine configurable GPIOs, and Reference-over-Reverse (RoR) clocking - all synchronized to the GMSL link without external reference. The device uses adaptive equalization (AEQ) and auto-adaptation to maintain signal integrity across aging cables and temperature extremes up to +105°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| GMSL Forward Rate | 3Gbps or 6Gbps per link - determines maximum supported sensor resolution and frame rate over single coax/STP cable. |
| GMSL Reverse Rate | 187.5Mbps - enables real-time sensor configuration, telemetry, and GPIO control without dedicated wires. |
| MIPI Output Format | D-PHY v1.2 (2.5Gbps/lane) or C-PHY v1.0 (5.7Gbps/lane) - selectable per port to match SoC receiver capability and bandwidth needs. |
| Operating Temp | −40°C to +105°C ambient - validated for under-hood and exterior camera placement in automotive applications. |
| Functional Safety | ASIL-B compliant (per MAX96724/F variant) - supports ISO 26262 requirements for fault detection and diagnostic coverage in ADAS systems. |
| Package | 56-pin TQFN-SW (8mm × 8mm, side-wettable) - enables automated optical inspection (AOI) and robust solder joint reliability in automotive reflow profiles. |
| Power-over-Coax | Integrated PoC support - eliminates separate power wiring for remote sensors, reducing harness weight and cost. |
Pinout & Package
MAX96724FGTN/VY+ uses a 56-pin TQFN-SW package (package code T5688Y+6C, outline 21-100046) with exposed pad for thermal dissipation. Side-wettable flanks enable post-solder AOI verification - critical for automotive production traceability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SIOA–SIOD | GMSL Serial Inputs | Four differential inputs accepting GMSL2/1 forward data; each independently configurable for tunnel/pixel mode and link rate. |
| DA/B_P/N, CKA/B/C/FP/N | MIPI CSI-2 Outputs | Dual-port MIPI lanes (Port A: 4-lane D/C-PHY; Port B: 4-lane D/C-PHY) - supports 2×4 or 4×2 lane routing with aggregation/replication. |
| I2C0_SDA/SCL, I2C1_SDA/SCL | Reverse-Channel I²C Ports | Two isolated I²C buses (≤1Mbps) for sensor register access and host-side diagnostics without interrupting video stream. |
| GPIO0–GPIO8 | Configurable Bidirectional I/O | Nine general-purpose pins usable as inputs (e.g., sync triggers) or outputs (e.g., LED control, reset assertion) via register programming. |
| REFCLK_IN, REFCLK_OUT | Reference Clock Interface | Supports RoR clocking: reference recovered from reverse channel and distributed to sensors, eliminating crystal at remote end. |
| PWDNB | Active-Low Power-Down | Hardware-controlled shutdown reducing quiescent current to <10μA; retains register state when asserted. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-adaptive equalization (AEQ) | Compensates for cable loss up to −21.0dB @ 3GHz (6Gbps), maintaining lock across aging, temperature drift, and connector wear. |
| MIPI D-PHY ↔ C-PHY conversion | Enables imager-side D-PHY sensors to interface directly with C-PHY SoCs - avoids external protocol bridge ICs and associated latency/power. |
| Video pipe aggregation/replication | Combines streams from up to four sensors into one CSI-2 port or duplicates one stream across two ports - simplifies multi-camera fusion architecture. |
| Reference-over-Reverse (RoR) | Delivers precise timing reference from SoC to remote sensors over same GMSL reverse channel - eliminates separate clock wiring and jitter accumulation. |
| ASIL-B functional safety support | Includes lock-detection, error-forwarding (EMB8), and diagnostic registers - reduces software validation effort for ISO 26262 ASIL-B compliance. |
Applications
| Front-Facing ADAS Camera | Rear-View Parking System |
|---|---|
Use Scenario: High-resolution (≥8MP) monocular camera mounted behind rearview mirror for forward collision warning and lane departure. IC Role / Device Role / Timing Role: Deserializes GMSL2 video from remote sensor and delivers aggregated MIPI CSI-2 stream to domain controller SoC with sub-frame sync. Use Value: Enables 6Gbps link for 4K@30fps capture with <1ms end-to-end latency, meeting NCAP timing requirements. |
Use Scenario: Multi-angle rear camera system using coax cabling through vehicle chassis to minimize EMI and harness complexity. IC Role / Device Role / Timing Role: Receives GMSL1/GMSL2 streams from up to four rear/side cameras and replicates selected feeds to display processor and ADAS ECU. Use Value: Reduces cable count by 75% vs. LVDS; supports simultaneous display and object detection on shared MIPI infrastructure. |
| Driver Monitoring System (DMS) | Surround-View System (SVS) |
Use Scenario: In-cabin IR camera operating at −40°C to +85°C ambient, requiring low-latency biometric data transfer. IC Role / Device Role / Timing Role: Deserializes GMSL2 tunnel-mode data containing eye-tracking metadata and raw IR frames to application processor. Use Value: Tunnel mode preserves embedded sensor-side processing results (e.g., pupil coordinates), avoiding reprocessing at SoC. |
Use Scenario: Four-corner camera fusion for 360° bird's-eye view, demanding precise inter-camera synchronization and low skew. IC Role / Device Role / Timing Role: Aggregates four GMSL2 inputs into single 4-lane MIPI port while maintaining frame-sync via dedicated VS/DE outputs. Use Value: Achieves <±5ns inter-lane skew and <100ns inter-sensor skew - critical for seamless stitching without motion artifacts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar GMSL deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX96724GTN/VY+ | Same die, standard TQFN (non-side-wettable); lacks AOI-compatible flanks. | Acceptable for non-automotive or lower-reliability industrial use where AOI is not mandated. | Select MAX96724FGTN/VY+ when automotive PPAP, AOI, or IPC-A-610 Class 3 solder joint verification is required. |
| MAX96717F | Single-input GMSL2 deserializer; no aggregation/replication; 2-lane MIPI output only. | Targeted at single-camera modules without multi-sensor coordination needs. | Choose MAX96724FGTN/VY+ when >1 sensor must be supported or MIPI lane count exceeds 2 per port. |
Compared with MAX96724GTN/VY+, the MAX96724FGTN/VY+ adds side-wettable flanks for automotive AOI compliance; compared with MAX96717F, it delivers quad-input scalability, dual-port MIPI flexibility, and full tunneling/aggregation - essential for scalable ADAS camera domain controllers.
Availability
MAX96724FGTN/VY+ is available at Aetrix Electronics and suitable for high-resolution camera systems, advanced driver assistance systems (ADAS), and surround-view applications requiring stable component supply, automotive-grade qualification, and long-term lifecycle support.
Supply support for MAX96724FGTN/VY+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving automotive, industrial, communications, and consumer markets with precision signal chain solutions.
The MAX96724FGTN/VY+ belongs to Analog Devices' GMSL serializer/deserializer product line, designed specifically for high-bandwidth, low-latency, functional-safety-compliant camera links in automotive ADAS and autonomous driving systems.
FAQ
What is the maximum supported cable length for MAX96724FGTN/VY+ at 6Gbps over 50Ω coax?
The MAX96724FGTN/VY+ supports up to 15 meters of 3.2mm Ø foam-dielectric 50Ω coax at 6Gbps/187.5Mbps under worst-case conditions (+105°C, aged cable). This is derived from its −21.0dB max insertion loss at 3.0GHz and integrated AEQ circuitry that compensates for channel degradation. Actual length depends on specific cable attenuation specs and environmental stress factors.
Does MAX96724FGTN/VY+ support both GMSL2 and GMSL1 protocols simultaneously?
Yes, the MAX96724FGTN/VY+ supports mixed GMSL2 and GMSL1 inputs - each of its four SIO inputs can be independently configured for GMSL2 (6/3Gbps) or GMSL1 (3.12Gbps) operation in either pixel or tunnel mode. This enables legacy sensor integration alongside newer GMSL2 devices within the same deserializer platform.
How many virtual channels does MAX96724FGTN/VY+ support for MIPI CSI-2?
The MAX96724FGTN/VY+ supports 16 virtual channels for D-PHY outputs and 32 virtual channels for C-PHY outputs. This enables multiplexing of multiple logical data streams (e.g., raw image, metadata, diagnostics) over a single physical MIPI lane set - critical for efficient bandwidth utilization in multi-function camera systems.
What reverse-channel resources are available on MAX96724FGTN/VY+?
The MAX96724FGTN/VY+ provides two I²C ports (I2C0/I2C1) supporting ≤1Mbps, nine configurable GPIOs (GPIO0–GPIO8), and Reference-over-Reverse (RoR) clock distribution. These resources allow full bidirectional control of remote sensors - including register read/write, firmware updates, sync signaling, and clock recovery - without additional wiring.
Is MAX96724FGTN/VY+ pin-compatible with other devices in the MAX967xx family?
No, the MAX96724FGTN/VY+ is not pin-compatible with other MAX967xx devices. Its 56-pin TQFN-SW footprint, MIPI lane assignment (dual 4-lane ports), and dedicated reverse-channel I/O allocation differ from variants like MAX96717F (32-pin) or MAX96705 (40-pin). Board redesign is required for substitution.
MAX96724FGTN/VY+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 56-WFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 6Gbps
- Input Type:
- GMSL
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- 4
- Number of Outputs:
- 2
- Voltage - Supply:
- 0.95V ~ 1.05V, 1.14V ~ 1.26V, 1.7V ~ 1.9V, 1.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 56-SWTQFN-EP (8x8)
MAX96724FGTN/VY+ FAQ
1.How can I place an order for MAX96724FGTN/VY+ through Aetrix?
Please submit a Request for Quotation (RFQ) for MAX96724FGTN/VY+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAX96724FGTN/VY+ reliable?
The price and inventory of MAX96724FGTN/VY+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAX96724FGTN/VY+ is usually 5 days.
3.What payment methods are accepted for MAX96724FGTN/VY+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAX96724FGTN/VY+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAX96724FGTN/VY+?
MAX96724FGTN/VY+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAX96724FGTN/VY+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAX96724FGTN/VY+?
For technical support, including MAX96724FGTN/VY+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAX96724FGTN/VY+ requirements.
6.How does Aetrix verify that MAX96724FGTN/VY+ is sourced from the original manufacturer or authorized distributors?
All MAX96724FGTN/VY+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAX96724FGTN/VY+ meets industry standards.
7.What is the process for return or replacement of MAX96724FGTN/VY+?
All MAX96724FGTN/VY+ units undergo pre-shipment inspection (PSI). If there is an issue with MAX96724FGTN/VY+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAX96724FGTN/VY+ part is unused and in its original packaging.
Return procedure for MAX96724FGTN/VY+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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