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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

onsemi MC100E336FN

Name: MC100E336FN
Brand: onsemi
SKU: MC100E336FN
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: MC100E336FN

Manufacturer:: onsemi

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: -

Datasheet:: MC100E336FN.pdf

Description:: REGISTERED BUS TRANSCEIVER

Quantity:: RFQ Add To RFQ list

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Product details

Overview

MC100E336FN from onsemi is a 5V ECL 3-bit registered bus transceiver with separate transmit and receive registers, 25 Ω cutoff bus outputs, 50 Ω receiver outputs, and dual-clock support (CLK1/CLK2). It operates in PECL mode (VCC = 4.2–5.7 V, VEE = 0 V) or NECL mode (VCC = 0 V, VEE = −4.2 to −5.7 V), delivering ≤1000 ps clock-to-Q and ≤1500 ps clock-to-bus propagation for high-speed backplane and data bus applications.

For engineers reviewing the MC100E336FN datasheet, pinout, applications, or equivalent options, key selection considerations include its dual-mode ECL operation, cutoff-output bus drive capability, internal edge-slow-down capacitors, register-controlled data flow, and PLCC-28 package with dedicated ground pins for noise-sensitive timing paths.

Technical Context

The MC100E336FN implements three independent ECL bus transceivers, each with synchronous transmit (A/B inputs → BUSn) and receive (BUSn → Qn) paths controlled by TEN, BUSEN, and RXEN enable signals. All registers are edge-triggered on rising CLK1 or CLK2, supporting asynchronous clocking across domains.

Its bus outputs feature true cutoff behavior (−2.0 V low state, high-impedance off-state) and integrated edge-slow-down capacitors to reduce EMI; receiver outputs are terminated to 50 Ω loads. Internal pulldown resistors on inputs and >1 kV HBM ESD protection enhance system robustness in industrial backplane environments.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	100E Series ECL - compatible with PECL (VCC = 4.2–5.7 V) and NECL (VEE = −4.2 to −5.7 V) supply configurations
Bus Outputs	25 Ω cutoff type - drives terminated buses with −2.0 V cutoff low state and high-Z off-state for wire-OR capability
Receiver Outputs	50 Ω ECL outputs - optimized for standard 50 Ω transmission line termination to VCC − 2.10 V
Propagation Delay	≤1000 ps clock-to-Q, ≤1500 ps clock-to-BUS - enables sub-1 ns timing margins in 100+ MHz synchronous bus systems
Supply Current	125–173 mA typical - stable over 0°C to +85°C, supporting thermally constrained backplane modules
Input Termination	Internal pulldown resistors - eliminates need for external biasing on A/B/TEN/RXEN/BUSEN inputs in unterminated stubs
ESD Rating	>1 kV HBM, >75 V MM - meets industrial handling requirements without additional protection circuitry

Pinout & Package

MC100E336FN is housed in a 28-lead Plastic Leaded Chip Carrier (PLCC-28), Case 776-02, with 12.57 mm × 12.57 mm body, 4.57 mm height, and 1.27 mm lead pitch. Ground pins (GND) are electrically isolated from die but provide mechanical grounding and RF shielding; all VCC/VCCO pins are internally tied.

Pin/Terminal	Circuit Role	Design Meaning
A0–A2, B0–B2	ECL data inputs (transmit source)	Dual-port input selection - A-side and B-side data routed to BUSn based on TEN control
TEN1, TEN2	Transmit enable	Low-active control: holds current data in transmit register or loads new A/B data on next clock edge
BUS0–BUS2	Cutoff bus outputs	25 Ω driver with −2.0 V cutoff low - presents high-Z when disabled, enabling multi-drop wired-OR bus topology
Q0–Q2	Receiver outputs	50 Ω ECL outputs - directly interface to 50 Ω-terminated receivers without external termination networks
RXEN	Receive enable	Low-active gate - allows bus data sampling only when asserted, preventing metastability on idle lines
BUSEN1, BUSEN2	Bus enable	Clocked disable - forces BUSn to −2.0 V cutoff state on next clock edge, synchronizing bus release
CLK1, CLK2	Positive-edge clock inputs	Redundant clock inputs - either or both trigger register updates, supporting clock domain crossing or redundancy
VCC, VCCO, VEE	Power supplies	VCC/VCCO tied internally; VEE referenced for NECL mode - all must be externally connected for guaranteed operation
GND	Package ground	Non-electrical die ground - provides mechanical stability and EMI shielding; must be soldered to PCB ground plane
NC	No connect	Pin 13 - unused; no internal connection; must remain unconnected

Key Features

Feature	Design Value
25 Ω cutoff bus outputs	Enables multi-drop wired-OR bus architectures without external pull-downs or bus contention logic
Internal edge-slow-down capacitors	Reduces signal overshoot/ringing on fast edges, lowering EMI in dense backplane layouts
Dual-clock register synchronization	Supports asynchronous clock domains via CLK1/CLK2 - simplifies timing closure in mixed-clock systems
PECL/NECL dual-mode operation	Single device supports both positive- and negative-ECL supply configurations - reduces BOM count in legacy/new designs
Isolated package ground pins	Provides mechanical grounding and RF shielding without introducing substrate noise coupling into sensitive ECL nodes

Applications

High-Speed Backplane Data Bus	Telecom Line Card Interconnect
Use Scenario: Synchronous data transfer between multiple line cards in a modular telecom chassis using shared parallel backplane traces. IC Role / Device Role / Timing Role: Registered bus transceiver - buffers and isolates A/B-side data, synchronizes bus writes/reads to system clock, and manages bus contention via BUSEN/RXEN. Use Value: Cutoff bus outputs prevent signal collisions during arbitration; 1000 ps clock-to-Q ensures tight setup/hold timing in 100+ MHz bus cycles.	Use Scenario: Interfacing FPGA-based packet processors to ASIC-based framer devices across a 25 Ω controlled-impedance backplane. IC Role / Device Role / Timing Role: ECL-level translator and register - converts internal FPGA logic levels to ECL-compatible signals while adding pipeline stages for timing margin. Use Value: Dual-mode operation allows reuse across PECL (FPGA side) and NECL (ASIC side); internal pulldowns eliminate external biasing on unterminated stubs.
Test Equipment Digital Pattern Generator	Industrial Real-Time Control Bus
Use Scenario: Generating precise, jitter-controlled stimulus patterns for high-speed digital IC validation at 100–200 MHz. IC Role / Device Role / Timing Role: Registered output driver - latches pattern data on CLK edge and drives low-skew, edge-controlled signals onto test fixture cables. Use Value: Edge-slow-down capacitors suppress reflections on 50 cm test leads; 1500 ps max clock-to-BUS guarantees deterministic launch timing.	Use Scenario: Connecting distributed I/O controllers in factory automation systems requiring deterministic latency and EMI resilience. IC Role / Device Role / Timing Role: Synchronized bus repeater - regenerates and retimes noisy field bus signals across long cable runs with clock-domain isolation. Use Value: Isolated GND pins reduce ground-loop noise; >1 kV HBM rating withstands industrial electrostatic discharge events without latch-up.

High-Speed Backplane Data Bus

Telecom Line Card Interconnect

Use Scenario: Synchronous data transfer between multiple line cards in a modular telecom chassis using shared parallel backplane traces.

IC Role / Device Role / Timing Role: Registered bus transceiver - buffers and isolates A/B-side data, synchronizes bus writes/reads to system clock, and manages bus contention via BUSEN/RXEN.

Use Value: Cutoff bus outputs prevent signal collisions during arbitration; 1000 ps clock-to-Q ensures tight setup/hold timing in 100+ MHz bus cycles.

Use Scenario: Interfacing FPGA-based packet processors to ASIC-based framer devices across a 25 Ω controlled-impedance backplane.

IC Role / Device Role / Timing Role: ECL-level translator and register - converts internal FPGA logic levels to ECL-compatible signals while adding pipeline stages for timing margin.

Use Value: Dual-mode operation allows reuse across PECL (FPGA side) and NECL (ASIC side); internal pulldowns eliminate external biasing on unterminated stubs.

Test Equipment Digital Pattern Generator

Industrial Real-Time Control Bus

Use Scenario: Generating precise, jitter-controlled stimulus patterns for high-speed digital IC validation at 100–200 MHz.

IC Role / Device Role / Timing Role: Registered output driver - latches pattern data on CLK edge and drives low-skew, edge-controlled signals onto test fixture cables.

Use Value: Edge-slow-down capacitors suppress reflections on 50 cm test leads; 1500 ps max clock-to-BUS guarantees deterministic launch timing.

Use Scenario: Connecting distributed I/O controllers in factory automation systems requiring deterministic latency and EMI resilience.

IC Role / Device Role / Timing Role: Synchronized bus repeater - regenerates and retimes noisy field bus signals across long cable runs with clock-domain isolation.

Use Value: Isolated GND pins reduce ground-loop noise; >1 kV HBM rating withstands industrial electrostatic discharge events without latch-up.

Equivalent & Alternatives

The following parts are listed as comparable options for similar ECL bus transceiver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC100E336FNG	Same die, green-compliant PLCC-28 (halogen-free, RoHS-compliant materials)	Identical electrical performance; required for EU/industrial environmental compliance	Select MC100E336FNG when RoHS/REACH compliance is mandatory; otherwise MC100E336FN remains suitable for non-regulated markets.
MC100LVEL336MNR4	LVDS input/output variant (3.3 V supply), no cutoff bus outputs, 1.2 ns clock-to-Q	Lower power, lower voltage; lacks wired-OR capability and ECL-level compatibility	Choose MC100LVEL336MNR4 only for new LVDS-based designs where ECL interoperability is unnecessary and power budget is constrained.

Compared with MC100E336FNG, the MC100E336FN offers identical timing and drive strength but lacks halogen-free certification; versus MC100LVEL336MNR4, it delivers true ECL-level signaling, cutoff bus architecture, and superior noise immunity - critical for legacy backplane upgrades and high-EMI environments.

Availability

MC100E336FN is available at Aetrix Electronics and suitable for high-speed backplane interconnects, telecom line card designs, and industrial real-time control systems requiring stable component supply, long-lifecycle support, and ECL-level signal integrity.

Supply support for MC100E336FN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient innovation, serving automotive, industrial, cloud, medical, and IoT markets with discrete, analog, and logic solutions.

The 100E Series was designed for high-speed ECL logic applications demanding sub-nanosecond timing, robust noise immunity, and dual-supply flexibility - targeting telecom infrastructure, test equipment, and military/aerospace computing.

FAQ

What supply configurations does the MC100E336FN support?

The MC100E336FN supports two distinct ECL operating modes: PECL mode with VCC = 4.2–5.7 V and VEE = 0 V, and NECL mode with VCC = 0 V and VEE = −4.2 to −5.7 V. Both configurations deliver identical timing and drive characteristics. All VCC, VCCO, and VEE pins must be externally connected to their respective supplies for guaranteed operation of the MC100E336FN.

How does the cutoff bus output functionality work on the MC100E336FN?

The MC100E336FN's BUS0–BUS2 outputs operate in cutoff mode: when driven LOW, they sink to −2.0 V and enter high-impedance state, effectively disconnecting from the bus. This enables wired-OR topologies and eliminates bus contention without external logic. The cutoff behavior is intrinsic to the MC100E336FN's ECL output stage and requires no configuration.

Can the MC100E336FN operate with only one clock input enabled?

Yes - the MC100E336FN's registers respond to the rising edge of either CLK1 or CLK2 (or both). Using only CLK1 or only CLK2 is fully supported and electrically identical; the dual-clock design provides redundancy and simplifies board layout in multi-clock systems. No configuration is needed to select a primary clock for the MC100E336FN.

What is the purpose of the isolated GND pins on the MC100E336FN PLCC package?

The GND pins on the MC100E336FN are mechanically grounded but not electrically connected to the silicon die. They serve to stabilize the PLCC package during reflow, improve thermal dissipation, and provide RF shielding against radiated emissions. These pins must be soldered to the PCB ground plane to realize their EMI suppression benefit in the MC100E336FN layout.

Does the MC100E336FN require external termination resistors?

The MC100E336FN's Q0–Q2 outputs are designed for 50 Ω termination to VCC − 2.10 V, and BUS0–BUS2 outputs require 25 Ω termination to VTT (typically VCC − 2.10 V). External resistors are mandatory for impedance matching and signal integrity - the MC100E336FN does not integrate termination. Application Note AND8020 details proper ECL termination practices for the MC100E336FN.

MC100E336FN Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Obsolete

Logic Type:: -

Number of Elements:: -

Number of Bits per Element:: -

Input Type:: -

Output Type:: -

Current - Output High, Low:: -

Voltage - Supply:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

MC100E336FN FAQ

1.How can I place an order for MC100E336FN through Aetrix?

Please submit a Request for Quotation (RFQ) for MC100E336FN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC100E336FN reliable?

The price and inventory of MC100E336FN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC100E336FN is usually 5 days.

3.What payment methods are accepted for MC100E336FN?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC100E336FN transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC100E336FN?

MC100E336FN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC100E336FN order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC100E336FN?

For technical support, including MC100E336FN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC100E336FN requirements.

6.How does Aetrix verify that MC100E336FN is sourced from the original manufacturer or authorized distributors?

All MC100E336FN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC100E336FN meets industry standards.

7.What is the process for return or replacement of MC100E336FN?

All MC100E336FN units undergo pre-shipment inspection (PSI). If there is an issue with MC100E336FN, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC100E336FN part is unused and in its original packaging.

Return procedure for MC100E336FN:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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