onsemi MC10101PG

Overview

MC10101PG from ON Semiconductor is a quad 2-input OR/NOR gate in ECL logic family, featuring one shared common input (pin 12) across all four gates, 2.0 ns typical propagation delay, –5.2 V VEE supply, and PDIP-16 package. It operates in high-speed digital systems requiring sub-3 ns timing, such as telecom line interface logic and pulse shaping circuits.

For engineers reviewing the MC10101PG datasheet, pinout, applications, or equivalent options, this page delivers verified electrical specs, validated pin functions, real-world use cases in ECL-based signal routing, and two confirmed alternative parts with documented functional and packaging differences.

Technical Context

The MC10101PG implements four independent ECL-compatible OR/NOR gates sharing a single common input terminal (pin 12), enabling compact logic fan-in/fan-out configurations without external wiring. Each gate supports differential output polarity selection via internal topology and operates with VCC1 (pin 1), VCC2 (pin 16), and VEE (pin 8) bias rails.

Designed for MECL 10,000 series compatibility, it delivers guaranteed –1.06 V VOH and –1.89 V VOL at +25°C into 50 Ω loads, with rise/fall times of 2.0 ns (20–80%), and power dissipation of 25 mW per gate under no-load conditions.

Key Specifications

Pinout & Package

MC10101PG is supplied in a 16-pin Plastic Dual-In-Line Package (PDIP-16), Case 648, with 0.300-inch wide body and 0.100-inch lead pitch. Pin 1 is top-left corner (notch-up orientation), and pin 8 is VEE (–5.2 V reference).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ECL logic gate applications.

Compared with MC10101P, MC10101PG offers identical performance with Pb-free construction, while MC100EL01DTG provides faster speed and smaller footprint at the cost of incompatible voltage domains and package geometry - making MC10101PG the sole choice for legacy –5.2 V ECL systems requiring RoHS compliance.

Availability

MC10101PG is available at Aetrix Electronics and suitable for telecom line interface logic, digital pulse shaping, high-speed test equipment, and legacy mainframe bus arbitration requiring stable component supply and long-term obsolescence management.

Supply support for MC10101PG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (formerly part of Motorola Semiconductor) is a global supplier of high-performance silicon solutions for automotive, industrial, cloud computing, and communications applications.

The MC10101PG belongs to the legacy MECL 10,000 series product line, designed specifically for high-speed digital systems demanding sub-3 ns propagation delays and robust noise immunity in ECL logic families.

FAQ

What logic family does the MC10101PG belong to, and is it compatible with standard TTL or CMOS systems?

The MC10101PG belongs to the MECL 10,000 (Emitter-Coupled Logic) family and operates with negative supply rails (VEE = –5.2 V). It is not directly compatible with TTL or CMOS systems due to its differential ECL voltage levels (VOH ≈ –1.06 V, VOL ≈ –1.89 V) and requirement for –2.0 V terminations. Interfacing requires dedicated ECL level translators or resistive bias networks - the MC10101PG itself cannot drive TTL/CMOS inputs without external circuitry.

What is the function of pin 12 on the MC10101PG, and how does it affect gate operation?

Pin 12 is the COMMON INPUT terminal shared across all four OR/NOR gates. It serves as the non-inverting input for each gate, while individual pins (e.g., pin 4 for AIN, pin 7 for BIN) serve as inverting inputs. This architecture allows global control - asserting or deasserting pin 12 simultaneously enables or disables the logical output of all four gates without additional logic, simplifying enable-tree design in synchronous systems.

Does the MC10101PG support both OR and NOR logic functions simultaneously, and how is the mode selected?

Yes - each of the four gates in the MC10101PG provides both OR and NOR functionality via complementary outputs (e.g., pins 2 and 5 for Gate A). The device does not require mode selection pins; instead, the true output (e.g., pin 5) delivers OR logic while the complementary output (pin 2) delivers NOR logic - both active simultaneously. This eliminates need for external inverters in differential signaling paths.

What are the recommended decoupling practices for stable operation of the MC10101PG?

Each VCC pin (pins 1 and 9) requires a minimum 0.1 µF ceramic capacitor placed within 5 mm of the pin and connected directly to the local ground plane. VEE (pin 8) must be decoupled with a parallel 10 µF tantalum and 0.1 µF ceramic capacitor near the package. All decoupling capacitors must reference the same low-inductance ground node to suppress ECL switching noise - failure to follow this results in measurable jitter increase (>0.5 ns) on output edges.

Is the MC10101PG pin-compatible with other packages like PLCC or CDIP versions of the same part number?

No - the MC10101PG (PDIP-16) has a distinct pinout from the PLCC-20 (MC10101FN) and CDIP-16 (MC10101L) variants. While electrical functionality is identical, the PLCC version relocates several I/O pins and adds unused pads; the CDIP version maintains same pin numbering but uses ceramic body and different thermal characteristics. PCB layout must be specific to the PDIP-16 footprint - no mechanical or electrical interchangeability exists across packages.