onsemi MC10104FN

Overview

MC10104FN from ON Semiconductor is a quad 2-input ECL AND gate in PLCC-20 package, featuring one gate with both AND and NAND outputs. It delivers 2.7 ns typical propagation delay, 2.0 ns typical rise/fall time (20–80%), and 35 mW typical power dissipation per gate-optimized for high-speed digital logic in telecom timing and test equipment.

For engineers reviewing the MC10104FN datasheet, pinout, applications, or equivalent options, key selection criteria include ECL-compatible voltage thresholds (VOH = –0.89 V, VOL = –1.85 V at +25°C), dual-output gate capability, PLCC-20 thermal and mounting constraints, and –5.2 V VEE supply requirement.

Technical Context

The MC10104FN implements four independent ECL 2-input AND gates using MECL 10,000 series bipolar technology, operating with negative supply (VEE = –5.2 V) and two positive rails (VCC1, VCC2). Its logic thresholds are referenced to VEE, enabling robust noise immunity in high-frequency clock distribution paths.

One gate (pins 12/13 inputs, 15/9 outputs) provides complementary AND/NAND outputs simultaneously-supporting differential signal routing without external inverters. All outputs drive 50 Ω loads terminated to –2.0 V, meeting standard ECL interface requirements for impedance-matched interconnects.

Key Specifications

Pinout & Package

MC10104FN uses a 20-pin Plastic Leaded Chip Carrier (PLCC-20, Case 775–02) with J-lead profile, 0.050" pitch, and 0.350" × 0.350" body. Seating plane defined by lead shoulder; mold flash ≤0.010" per side.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ECL logic gate applications.

Compared with MC10104FN, MC100EL04DTG saves board area but adds design complexity for differential outputs, while SN65EL104P offers measurable timing improvement and supply robustness without layout change-making it the preferred upgrade path where performance headroom is critical.

Availability

MC10104FN is available at Aetrix Electronics and suitable for telecom infrastructure, high-speed test instrumentation, and RF transceiver control applications requiring stable component supply across extended product lifecycles.

Supply support for MC10104FN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (now onsemi) is a global semiconductor supplier focused on energy-efficient electronics, delivering power management, analog, sensor, and logic solutions.

The MC10104FN belongs to the legacy MECL 10,000 series logic family, engineered for high-speed, low-jitter digital signal routing in telecom, military, and instrumentation systems where ECL's deterministic timing is essential.

FAQ

What is the recommended termination for MC10104FN outputs?

MC10104FN outputs must be terminated with a 50 Ω resistor to –2.0 V, as specified in the datasheet's switching times test conditions. This termination ensures proper ECL signal integrity, controls reflections on PCB traces, and maintains the 2.7 ns propagation delay and 2.0 ns edge rates. Using alternative terminations (e.g., open-drain or Thevenin) will degrade timing performance and may cause logic errors in high-speed systems.

Does MC10104FN require decoupling capacitors, and if so, what values?

Yes, MC10104FN requires local decoupling: a 0.1 µF ceramic capacitor between each VCC pin (1 and 16) and VEE (pin 8), placed within 5 mm of the device. This suppresses high-frequency supply noise generated by rapid ECL switching (2.0 ns edges), preventing ground bounce and output instability. Bulk capacitance (e.g., 10 µF tantalum) near the VEE rail entry point is also recommended for system-level stability.

Can MC10104FN operate with VEE = –4.5 V instead of –5.2 V?

No-MC10104FN is characterized and guaranteed only at VEE = –5.2 V, as confirmed by all electrical specifications (VOH, VOL, tpd, IE) in the datasheet. Operating at –4.5 V shifts thresholds outside specification, increases propagation delay beyond 2.7 ns, and risks incorrect logic states. For variable VEE operation, consider SN65EL104P, which supports –4.5 V to –5.5 V.

Which pins provide the dual AND/NAND output on MC10104FN?

On MC10104FN, Gate 1 provides dual outputs: pin 15 is the AND output and pin 9 is the NAND output. This is explicitly shown in the logic diagram and pin assignment table. Pins 14, 2, 3, and 11 serve as the single-ended AND outputs for Gates 2–4. No other gate in the MC10104FN offers complementary outputs.

Is MC10104FN RoHS compliant?

MC10104FN (PLCC-20, FN suffix) was manufactured prior to RoHS enforcement and is not RoHS compliant-it contains lead in the solder plating and die attach. For RoHS-compliant alternatives, consult onsemi's current EL or ECL families (e.g., MC100EP04), which offer functionally similar quad AND gates in lead-free PLCC-20 packages with updated environmental compliance.