onsemi MC10104L

Overview

MC10104L from ON Semiconductor is a quad 2-input ECL AND gate with one gate providing both AND and NAND outputs, 2.7 ns typical propagation delay, 2.0 ns typical rise/fall time (20–80%), and 35 mW typical power dissipation per gate-designed for high-speed logic interfacing in telecom line cards and test equipment.

For engineers reviewing the MC10104L datasheet, pinout, applications, or equivalent options, this page delivers verified electrical specs, CDIP-16 package details, MECL 10K-series timing behavior, and direct alternatives for legacy ECL system upgrades.

Technical Context

The MC10104L operates in negative ECL (NECL) mode with V_EE = –5.2 V, V_CC1 = V_CC2 = GND, and logic thresholds centered near –0.91 V (V_OHA) and –1.63 V (V_OLA). All four gates share identical DC and AC characteristics except Gate 1, which provides complementary outputs on Pins 15 (AND) and 9 (NAND).

Switching performance is specified under 50 Ω load termination to –2.0 V, with propagation delays measured between input (e.g., Pin 12/13) and output (e.g., Pin 15/9), and rise/fall times defined at 20–80% of swing across –0.89 V to –1.89 V.

Key Specifications

Pinout & Package

Ceramic Dual-In-Line Package (CDIP-16), Case 620-10, hermetically sealed, lead spacing 0.100", body size 0.750" × 0.240", suitable for high-reliability military/aerospace and telecom applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ECL logic gate applications.

Compared with MC10104P and SN10104J, the MC10104L offers superior thermal stability and hermetic reliability for aerospace and telecom infrastructure, while SN10104J provides seamless sourcing continuity where ON Semi supply is constrained.

Availability

MC10104L is available at Aetrix Electronics and suitable for telecom line card timing, high-speed test equipment, digital signal processing backplanes, and military avionics data buses requiring stable component supply over extended product lifecycles.

Supply support for MC10104L includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (formerly part of Motorola Semiconductor) is a global supplier of high-performance silicon solutions for automotive, industrial, cloud computing, and communications markets.

The MC10104L belongs to the legacy MECL 10K logic family, designed specifically for ultra-high-speed digital systems requiring sub-nanosecond timing precision and ECL-level noise immunity.

FAQ

What logic family does the MC10104L belong to, and is it compatible with other MECL devices?

The MC10104L belongs to the MECL 10K (10,000-series) family and is fully compatible with other MECL 10K devices such as the MC10116 and MC10132. Its V_OHA = –0.91 V and V_OLA = –1.63 V thresholds, –5.2 V V_EE supply, and 50 Ω load termination requirements align precisely with the MECL 10K standard. The MC10104L can directly interface with these parts without level-shifting circuitry.

Does the MC10104L require external termination resistors, and if so, where are they placed?

Yes, the MC10104L requires 50 Ω termination to –2.0 V on all outputs (e.g., Pins 2, 3, 6, 9, 14, 15) to meet specified switching times and waveform integrity. This termination is mandatory per the datasheet test condition and ensures 2.0 ns rise/fall times and 2.7 ns propagation delay. Without proper termination, the MC10104L exhibits degraded timing and increased jitter.

Which pins provide complementary outputs on the MC10104L, and how are they used?

Only Gate 1 of the MC10104L provides complementary outputs: Pin 15 is the AND output and Pin 9 is the NAND output. These two pins deliver logically inverted signals from the same gate pair (Inputs on Pins 12 and 13), enabling wired-OR logic, dynamic logic trees, and reduced gate count in combinatorial circuits - a unique capability not available on Gates 2–4 of the MC10104L.

What is the operating temperature range for the MC10104L, and how does it compare to the MC10104P?

The MC10104L is specified for –30°C to +85°C operation, validated across that full range per its CDIP-16 hermetic package. In contrast, the MC10104P (plastic DIP) is rated only from 0°C to +70°C. This makes the MC10104L suitable for under-hood automotive, base station, and avionics applications where extended temperature performance is mandatory - a key differentiator of the MC10104L.

Can the MC10104L be used with modern FPGAs or microcontrollers, and what interface considerations apply?

The MC10104L cannot interface directly with modern CMOS or LVDS I/O due to its negative ECL voltage levels (–0.89 V to –1.89 V). To connect to FPGAs or microcontrollers, level translation is required - typically using dedicated ECL-to-CMOS translators like the MC100ELT20 or resistor-based bias networks. The MC10104L remains relevant only in legacy ECL systems or hybrid backplanes where its speed and noise immunity justify the interface complexity.