onsemi MC10105FNR2

Overview

MC10105FNR2 from ON Semiconductor is a triple 2–3–2-input OR/NOR gate in ECL logic family, designed for high-speed digital signal routing in timing-critical systems. It delivers 2.0 ns typical propagation delay, 2.0 ns typical rise/fall time (20%–80%), and 30 mW typical power dissipation per gate, operating with V_EE = –5.2 V and dual V_CC supplies. It is used in telecom line card clock distribution and high-frequency test equipment logic steering.

For engineers reviewing the MC10105FNR2 datasheet, pinout, applications, or equivalent options, this page provides verified functional identity, PLCC-20 package mapping, confirmed ECL voltage thresholds (V_OHA = –1.105 V min at +25°C), output swing (–1.06 V to –1.89 V), and validated alternative options for MECL 10,000-series logic replacement.

Technical Context

The MC10105FNR2 implements three independent OR/NOR logic gates with asymmetric input configurations: Gate A accepts two inputs, Gate B accepts three, and Gate C accepts two - all sharing common V_CC1, V_CC2, and V_EE rails. Each gate drives into 50 Ω loads terminated to –2.0 V, meeting MECL 10,000 series DC specifications across –30°C to +85°C.

Its switching behavior is characterized by matched t_pd (2.0 ns typ), t_r/t_f (2.0 ns typ), and tightly controlled VOH/VOL windows (–1.060 V to –0.700 V and –1.890 V to –1.615 V), enabling deterministic timing in multi-gate fanout chains without external termination resistors beyond the standard 50 Ω load.

Key Specifications

Pinout & Package

MC10105FNR2 is supplied in a 20-lead plastic leaded chip carrier (PLCC-20), case 775–02, with gull-wing leads and JEDEC-standard footprint. Pin 1 is marked with a dot; seating plane defined by lead shoulder datum –T–.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ECL logic gate applications.

Compared with MC10105FNR2, the MC10105P offers identical logic performance in a through-hole format ideal for breadboarding, while the MC10105L adds ceramic hermeticity and wider temperature margin - neither is pin-compatible with the PLCC-20 MC10105FNR2, requiring PCB layout revision for substitution.

Availability

MC10105FNR2 is available at Aetrix Electronics and suitable for telecom infrastructure, high-speed test instrumentation, and industrial data acquisition systems requiring stable component supply and long-term obsolescence management.

Supply support for MC10105FNR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (now part of onsemi) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensor solutions for automotive, industrial, and communications markets.

The MC10105FNR2 belongs to the legacy MECL 10,000 series logic family, engineered specifically for ultra-high-speed digital signal routing in telecom and instrumentation systems where nanosecond-level timing determinism is mandatory.

FAQ

What logic family does the MC10105FNR2 belong to, and what supply voltages does it require?

The MC10105FNR2 is a MECL 10,000-series ECL device requiring V_EE = –5.2 V and dual positive V_CC supplies (pins 1 and 16). It operates with input thresholds centered around –1.1 V (logic 1) and –1.5 V (logic 0), and its outputs swing between –1.06 V and –1.89 V under 50 Ω load. This configuration ensures interoperability with other MECL 10K components in legacy timing systems. The MC10105FNR2 must not be powered with TTL or CMOS supply schemes.

Is the MC10105FNR2 pin-compatible with other MC10105 variants like MC10105P or MC10105L?

No, the MC10105FNR2 is not pin-compatible with MC10105P (PDIP-16) or MC10105L (CDIP-16). The MC10105FNR2 uses a 20-lead PLCC package with different pin count, spacing, and terminal assignment - including dedicated V_CC1/V_CC2 separation and unused PLCC pads. Substituting any variant requires PCB redesign. The MC10105FNR2's pinout follows ON Semiconductor's PLCC-20 conversion table, distinct from DIP layouts.

What is the maximum operating temperature range for the MC10105FNR2, and how does performance change across that range?

The MC10105FNR2 is rated for operation from –30°C to +85°C. Electrical characteristics shift predictably: VOH degrades from –1.060 V (min at –30°C) to –0.700 V (min at +85°C); VOL shifts from –1.890 V to –1.615 V. Propagation delay remains stable at 2.0 ns typical across the range, but worst-case t_pd increases to 3.3 ns at +85°C. These variations are fully characterized in the official ON Semiconductor datasheet for MC10105FNR2.

Can the MC10105FNR2 drive 50 Ω transmission lines directly, and what termination is required?

Yes, the MC10105FNR2 is designed to drive 50 Ω loads terminated to –2.0 V - a standard configuration for ECL signaling. Its output stage delivers specified VOH/VOL levels only under this condition. No series resistor is needed at the source; however, unterminated traces longer than 1 inch will cause reflections. For point-to-point routing, a single 50 Ω resistor from each output to –2.0 V is mandatory. The MC10105FNR2 does not support open-emitter or current-mode logic (CML) configurations.

Does the MC10105FNR2 support mixed logic families, such as interfacing with TTL or LVDS devices?

No, the MC10105FNR2 is strictly an ECL device and lacks level-shifting circuitry. Its –1.06 V to –1.89 V output swing and negative-referenced inputs are incompatible with TTL (0 V / +5 V), CMOS (+0.3 V / +3.3 V), or LVDS (±0.35 V) interfaces without external translation. Direct connection risks latch-up or undefined states. Interface to non-ECL systems requires discrete level translators or dedicated ECL-to-LVDS ICs. The MC10105FNR2 functions correctly only within MECL 10K ecosystems.