Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi MC10109P

Name: MC10109P
Brand: onsemi
SKU: MC10109P
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: MC10109P

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: -

Datasheet:: MC10109P.pdf

Description:: IC GATE OR/NOR

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,195

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

MC10109P from ON Semiconductor is a dual 4–5-input ECL OR/NOR gate IC designed for high-speed logic interfacing in telecom and instrumentation systems. It delivers 2.0 ns typical propagation delay, 2.0 ns typical rise/fall time (20%–80%), and 30 mW typical power dissipation per gate with ±5.2 V supplies (V_CC = –0.89 V, V_EE = –5.2 V) at +25°C.

For engineers reviewing the MC10109P datasheet, pinout, applications, or equivalent options, this page provides verified electrical parameters, PDIP-16 package mapping, functional role in ECL logic trees, and validated alternative parts for timing-critical digital designs.

Technical Context

The MC10109P implements two independent ECL gates: one with four inputs (A1–A4) configured as OR/NOR, and another with five inputs (B1–B5) similarly configurable. Each gate operates with negative logic swing between –0.89 V (VOH) and –1.85 V (VOL) under 50 Ω load termination to –2.0 V.

It requires dual supply rails: V_CC1 (Pin 1) and V_CC2 (Pin 16) at –0.89 V nominal, and V_EE (Pin 8) at –5.2 V. Input thresholds are VIHA = –1.105 V and VILA = –1.475 V at +25°C, enabling robust noise margin in high-frequency ECL signal chains.

Key Specifications

Parameter	Value and Actual Design Meaning
Propagation Delay	2.0 ns typ - ensures sub-500 MHz clock domain compatibility in ECL logic families
Rise/Fall Time	2.0 ns typ (20–80%) - supports clean edge integrity on 50 Ω transmission lines
Power Dissipation	30 mW typ/gate - enables dense placement without thermal derating in multi-gate arrays
Output Voltage Logic 1	–0.890 Vdc min at +25°C - compatible with standard MECL 10K input thresholds
Output Voltage Logic 0	–1.850 Vdc max at +25°C - maintains >0.9 V noise margin against V_EE = –5.2 V rail
Input Threshold Logic 1	–1.105 Vdc min (VIHA) - defines switching point for reliable high-to-low transition detection
Supply Configuration	V_CC1/V_CC2 = –0.89 V, V_EE = –5.2 V - standard MECL 10K biasing for interoperability

Pinout & Package

MC10109P is supplied in a 16-pin plastic dual-in-line package (PDIP-16), Case 648–08, with 0.300-inch width and 0.100-inch lead pitch. Pin 1 is V_CC1, Pin 16 is V_CC2, and Pin 8 is V_EE. Outputs are complementary (AOUT/AOUT, BOUT/BOUT) for differential signaling.

Pin/Terminal	Circuit Role	Design Meaning
1	V_CC1	Negative V_CC supply for Gate A (–0.89 V nominal)
2, 3	AOUT, AOUT	Differential outputs of 4-input OR/NOR Gate A
4–7	AIN1–AIN4	Four inputs to Gate A (ECL-compatible, VIHA/VILA referenced)
8	V_EE	Negative supply rail (–5.2 V) common to both gates
9, 10	BOUT, BOUT	Differential outputs of 5-input OR/NOR Gate B
11–15	BIN1–BIN5	Five inputs to Gate B (fully ECL 10K compliant)
16	V_CC2	Negative V_CC supply for Gate B (–0.89 V nominal)

Key Features

Feature	Design Value
Dual independent ECL gates	One 4-input and one 5-input OR/NOR function in single PDIP-16 package
High-speed performance	2.0 ns propagation delay enables use in >400 MHz logic paths
Standard MECL 10K compatibility	Fully interoperable with MC10100-series devices using identical V_CC/V_EE and threshold specs
Differential output pairs	AOUT/AOUT and BOUT/BOUT support noise-immune routing and termination
Low-power ECL operation	30 mW/gate allows integration of multiple gates without excessive board-level heating

Applications

Telecom Line Card Timing	High-Speed Test Equipment
Use Scenario: Generating synchronized enable signals across multiple DS3/E3 framers in a line card. IC Role / Device Role / Timing Role: Dual OR/NOR gate providing programmable logic enable/disable control with sub-2.5 ns skew. Use Value: Matches MECL 10K timing budgets and eliminates need for discrete resistor-terminated TTL translators.	Use Scenario: Implementing pattern generation logic in automated test equipment (ATE) stimulus modules. IC Role / Device Role / Timing Role: Fast combinational logic block for real-time test vector sequencing and pass/fail decision gating. Use Value: 2.0 ns t_pd ensures deterministic setup/hold margins for 500 Mbps parallel data paths.
Radar Signal Processing	Digital Oscilloscope Trigger Path
Use Scenario: Combining pulse detection outputs from multiple ADC channels in phased-array radar front ends. IC Role / Device Role / Timing Role: High-speed OR function aggregating asynchronous event flags with minimal added jitter. Use Value: Differential outputs interface directly to ECL comparators and latch arrays without level-shifting.	Use Scenario: Constructing complex trigger conditions (e.g., "A AND NOT B OR C") in real-time oscilloscope acquisition engines. IC Role / Device Role / Timing Role: Combinational logic element in ultra-low-latency trigger decision tree. Use Value: Sub-2 ns delay preserves picosecond-level timing correlation between analog capture and trigger assertion.

Telecom Line Card Timing

High-Speed Test Equipment

Use Scenario: Generating synchronized enable signals across multiple DS3/E3 framers in a line card.

IC Role / Device Role / Timing Role: Dual OR/NOR gate providing programmable logic enable/disable control with sub-2.5 ns skew.

Use Value: Matches MECL 10K timing budgets and eliminates need for discrete resistor-terminated TTL translators.

Use Scenario: Implementing pattern generation logic in automated test equipment (ATE) stimulus modules.

IC Role / Device Role / Timing Role: Fast combinational logic block for real-time test vector sequencing and pass/fail decision gating.

Use Value: 2.0 ns t_pd ensures deterministic setup/hold margins for 500 Mbps parallel data paths.

Radar Signal Processing

Digital Oscilloscope Trigger Path

Use Scenario: Combining pulse detection outputs from multiple ADC channels in phased-array radar front ends.

IC Role / Device Role / Timing Role: High-speed OR function aggregating asynchronous event flags with minimal added jitter.

Use Value: Differential outputs interface directly to ECL comparators and latch arrays without level-shifting.

Use Scenario: Constructing complex trigger conditions (e.g., "A AND NOT B OR C") in real-time oscilloscope acquisition engines.

IC Role / Device Role / Timing Role: Combinational logic element in ultra-low-latency trigger decision tree.

Use Value: Sub-2 ns delay preserves picosecond-level timing correlation between analog capture and trigger assertion.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ECL logic applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MC10107P	Single 4-input OR/NOR gate, same PDIP-16 package and timing (2.0 ns t_pd), but no second gate	Requires two ICs to replicate dual functionality; increases board area and interconnect skew	Select when only one gate is needed and layout space is constrained
MC10110P	Dual 2-input OR/NOR gate; faster (1.7 ns t_pd) but fewer inputs per gate (2 vs. 4/5)	Needs cascading for multi-input logic, adding 1.7–3.4 ns cumulative delay and extra loading	Select when logic depth is shallow and maximum speed per stage is critical

Compared with MC10107P and MC10110P, the MC10109P uniquely balances input count (4+5), dual-gate integration, and 2.0 ns timing-making it optimal for compact, multi-input ECL combinatorial logic where gate count and propagation latency must both be minimized.

Availability

MC10109P is available at Aetrix Electronics and suitable for telecom infrastructure, high-speed test equipment, and radar signal processing requiring stable component supply and long-term obsolescence management.

Supply support for MC10109P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor (now part of onsemi) is a global semiconductor supplier specializing in energy-efficient power, analog, sensing, and connectivity solutions.

The MC10109P belongs to the legacy MECL 10K logic family, engineered for high-speed digital systems demanding sub-nanosecond timing precision and ECL-level noise immunity in telecom and instrumentation.

FAQ

What logic family does the MC10109P belong to?

The MC10109P is a member of the MECL 10K (Motorola Emitter-Coupled Logic) family. It operates with negative voltage supplies (V_CC ≈ –0.89 V, V_EE = –5.2 V), delivers ECL-compatible output swings, and meets all DC and AC specifications defined for the MECL 10K standard. The MC10109P is fully interoperable with other MC101xx-series devices in mixed-gate logic designs.

What is the recommended termination for MC10109P outputs?

MC10109P outputs must be terminated with a 50 Ω resistor to –2.0 V, as specified in the official ON Semiconductor datasheet. This termination ensures proper signal integrity, minimizes reflections on PCB traces, and guarantees the 2.0 ns propagation delay and 2.0 ns rise/fall time performance. Failure to use –2.0 V termination will degrade timing and increase jitter in high-speed applications.

Can MC10109P operate with a single supply rail?

No, the MC10109P requires two distinct supply connections: V_CC1 (Pin 1), V_CC2 (Pin 16), and V_EE (Pin 8). These are not interchangeable - V_CC pins source current at approximately –0.89 V, while V_EE sinks current at –5.2 V. Using a single rail violates the internal transistor biasing scheme and will prevent correct logic operation of the MC10109P.

Is MC10109P pin-compatible with MC10109L or MC10109FN?

No - MC10109P (PDIP-16), MC10109L (CDIP-16), and MC10109FN (PLCC-20) share identical logic functionality and electrical specs but differ in physical package and pinout. The PLCC-20 version has different pin assignments (see ON Semiconductor DL122/D pin conversion tables), and the ceramic DIP uses alternate leadform. Only the PDIP-16 variant matches the MC10109P pin map exactly.

What is the maximum operating temperature for MC10109P?

The MC10109P is characterized for operation from –30°C to +85°C, with full electrical specifications guaranteed across this range. At +85°C, propagation delay increases to 2.9 ns max (vs. 2.0 ns typ at +25°C), and output voltage levels shift slightly (VOH = –0.700 V, VOL = –1.615 V). Thermal design must ensure junction temperature remains within this limit for sustained reliability of the MC10109P.

MC10109P Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Active

Logic Type:: -

Number of Circuits:: -

Number of Inputs:: -

Features:: -

Voltage - Supply:: -

Current - Quiescent (Max):: -

Current - Output High, Low:: -

Input Logic Level - Low:: -

Input Logic Level - High:: -

Max Propagation Delay @ V, Max CL:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

MC10109P FAQ

1.How can I place an order for MC10109P through Aetrix?

Please submit a Request for Quotation (RFQ) for MC10109P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for MC10109P reliable?

The price and inventory of MC10109P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MC10109P is usually 5 days.

3.What payment methods are accepted for MC10109P?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MC10109P transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for MC10109P?

MC10109P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your MC10109P order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for MC10109P?

For technical support, including MC10109P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MC10109P requirements.

6.How does Aetrix verify that MC10109P is sourced from the original manufacturer or authorized distributors?

All MC10109P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MC10109P meets industry standards.

7.What is the process for return or replacement of MC10109P?

All MC10109P units undergo pre-shipment inspection (PSI). If there is an issue with MC10109P, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The MC10109P part is unused and in its original packaging.

Return procedure for MC10109P:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…